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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-02-14 01:52:56 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-02-21 00:24:26 +0300 |
| commit | 2846cf3fdb8b500e374efdcad3134633dcc5ce60 (patch) | |
| tree | 211da5de80f2b1fdd94d373a10d1ad57ffae2cbf /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | bfa5969e1144c8d0fbbe1a976601dcbc50549757 (diff) | |
| download | linux-2846cf3fdb8b500e374efdcad3134633dcc5ce60.tar.xz | |
drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+
On TGL VBLANK.VBLANK_START was the mechanism by which we can
delay the pipe's internal vblank in relation to the transcoder's
vblank. On ADL+ that no longer does anything. Instead we must
now use the new TRANS_SET_CONTEXT_LATENCY register. Program it
accordingly.
And since VBLANK.VBLANK_START is no longer used by the hardware
on ADL+ let's just zero it out to make it stand out in register
dumps. Seeing the zeroed value should hopefully remind people
to check the other register instead.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-11-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions