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| author | Madhav Chauhan <madhav.chauhan@intel.com> | 2018-07-05 16:49:36 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2018-07-06 12:14:16 +0300 |
| commit | 166869b390b6fe763544fe4ae1e01acd28db331a (patch) | |
| tree | 7ed33ce5253ac86e775bc0e6f51877b9f01afe02 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | b1cb21a5f1c668534b25464717c806e141ba500f (diff) | |
| download | linux-166869b390b6fe763544fe4ae1e01acd28db331a.tar.xz | |
drm/i915/icl: Define PORT_CL_DW_10 register
This register used to power down individual lanes for
DDI/DSI ports. Bitfields to power up/down various
combinations of lanes are also added in this patch.
v2: Review comments from Jani N
- Use override instead of "override" for bitfields
- Define mask for override bitfield
- Define PWR_DOWN_LN* macros shifted in place
v3: Correct PWR_DOWN_LN_MASK value (Jani N)
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530798591-2077-6-git-send-email-madhav.chauhan@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions