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authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>2023-03-01 23:10:49 +0300
committerRadhakrishna Sripada <radhakrishna.sripada@intel.com>2023-03-09 20:40:17 +0300
commit0188be507b973e36f637ba010a369057c8cb7282 (patch)
tree82be942bda5816b14feb1a5d611cfbd36e1d67c6 /tools/perf/scripts/python/export-to-postgresql.py
parent4b736ed40583631e0cf32c55dbc1e5ec0434a74b (diff)
downloadlinux-0188be507b973e36f637ba010a369057c8cb7282.tar.xz
drm/i915/mtl: Fix Wa_16015201720 implementation
The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds") extended the workaround Wa_16015201720 to MTL. However the registers that the original WA implemented moved for MTL. Implement the workaround with the correct register. v3: Skip clock gating for pipe C, D DMC's and fix the title Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds") Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301201053.928709-2-radhakrishna.sripada@intel.com
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