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| author | David Lechner <dlechner@baylibre.com> | 2025-02-07 23:09:07 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2025-02-10 21:48:48 +0300 |
| commit | 503d20ed8cf7c7b40ec0bd94f53c490c1d91c31b (patch) | |
| tree | 31b8123505ed8948c0db8a699fa8398581d7ec79 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 79f24971b4ffbdba9733365e298982c45338e6b1 (diff) | |
| download | linux-503d20ed8cf7c7b40ec0bd94f53c490c1d91c31b.tar.xz | |
iio: adc: ad7944: don't use storagebits for sizing
Replace use of storagebits with realbits for determining the number of
bytes needed for SPI transfers.
When adding SPI offload support, storagebits will always be 32 rather
than 16 for 16-bit 16-bit chips so we can no longer rely on storagebits
being the correct size expected by the SPI framework (it always uses
4 bytes for > 16-bit xfers and 2 bytes for > 8-bit xfers). Instead,
derive the correct size from realbits since it will always be correct
even when SPI offloading is used.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-vy: Nuno Sa <nuno.sa@analog.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-10-e48a489be48c@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions