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| author | Aditya Swarup <aditya.swarup@intel.com> | 2021-01-25 17:07:48 +0300 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2021-01-26 18:10:45 +0300 |
| commit | 80d0f76588b55e5226d65776bb5fca7360837f1d (patch) | |
| tree | ba86585ed29c833966f3adf4895da3dd54f32e22 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | a84b4bd1172b8394d5540b51b3cf0f76c0dff17a (diff) | |
| download | linux-80d0f76588b55e5226d65776bb5fca7360837f1d.tar.xz | |
drm/i915/adl_s: Configure DPLL for ADL-S
Add changes for configuring DPLL for ADL-S
- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
- Extend CNL macro to choose DPLL_ENABLE
for ADL-S.
- Select CFGCR0 and CFGCR1 for ADL-S plls.
On BSpec: 53720 PLL arrangement dig for adls:
DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)
v2 (Lucas): add missing update_ref_clks
Bspec: 50288
Bspec: 50289
Bspec: 49443
v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield
for DPLL3_USED.(mdroper)
Bspec: 53707
v4: BSpec 53723 has been updated with note - DPLL2 is
controlled by DPLL4 CFGCR 0/1.(mdroper)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-6-aditya.swarup@intel.com
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions