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| author | Ian Rogers <irogers@google.com> | 2024-06-20 21:17:35 +0300 |
|---|---|---|
| committer | Namhyung Kim <namhyung@kernel.org> | 2024-06-21 02:54:59 +0300 |
| commit | 025cce253b9fde9619c635832b1f86df559f8d5d (patch) | |
| tree | 497e07c945aa5fcfa6f1ee058c32094db1e53d23 /tools/perf/pmu-events/arch/x86/knightslanding/frontend.json | |
| parent | 8791622572df8f0077351b8b6e5b56f938126ed1 (diff) | |
| download | linux-025cce253b9fde9619c635832b1f86df559f8d5d.tar.xz | |
perf vendor events: Add knightslanding counter information
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-22-irogers@google.com
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/knightslanding/frontend.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/knightslanding/frontend.json | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json index 9001f5019848..63343a0d1e86 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.ALL", "SampleAfterValue": "200003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.COND", "SampleAfterValue": "200003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.RETURN", "SampleAfterValue": "200003", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Counts all instruction fetches, including uncacheable fetches.", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200003", @@ -29,6 +33,7 @@ }, { "BriefDescription": "Counts all instruction fetches that hit the instruction cache.", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "200003", @@ -36,6 +41,7 @@ }, { "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200003", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Counts the number of times the MSROM starts a flow of uops.", + "Counter": "0,1", "EventCode": "0xE7", "EventName": "MS_DECODED.MS_ENTRY", "SampleAfterValue": "200003", |