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authorJean-Philippe Brucker <jean-philippe@linaro.org>2022-09-16 16:31:47 +0300
committerJoerg Roedel <jroedel@suse.de>2022-09-26 15:05:58 +0300
commitd2f2f1d10ccdb96aeea38c5ec647679fcc093b84 (patch)
treeddccaddc3d45261b6042391980e335639a3be634 /sound/soc/sof/ipc4-control.c
parent7e18e42e4b280c85b76967a9106a13ca61c16179 (diff)
downloadlinux-d2f2f1d10ccdb96aeea38c5ec647679fcc093b84.tar.xz
dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names
The QEMU devicetree uses a different order for SMMUv3 interrupt names, and there isn't a good reason for enforcing a specific order. Since all interrupt lines are optional, operating systems should not expect a fixed interrupt array layout; they should instead match each interrupt to its name individually. Besides, as a result of commit e4783856a2e8 ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync" and "priq" are already permutable. Relax the interrupt-names array entirely by allowing any permutation, incidentally making the schema more readable. Note that dt-validate won't allow duplicate names here so we don't need to specify maxItems or add additional checks, it's quite neat. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Acked-by: Will Deacon <will@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220916133145.1910549-1-jean-philippe@linaro.org Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'sound/soc/sof/ipc4-control.c')
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