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| author | Padmavathi Venna <padma.v@samsung.com> | 2014-11-07 09:54:40 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2014-11-07 13:41:22 +0300 |
| commit | a5a56871f804edac93a53b5e871c0e9818fb9033 (patch) | |
| tree | b5d9183ac7f4cd32d4f59f9bc305432d0fbc738b /sound/soc/samsung/i2s-regs.h | |
| parent | b07597367001c2c4f36a97863530f71b84060d3d (diff) | |
| download | linux-a5a56871f804edac93a53b5e871c0e9818fb9033.tar.xz | |
ASoC: samsung: add support for exynos7 I2S controller
Exynos7 I2S controller has no internal dma, supports more
no. of root clock sampling frequencies and has more no.of Rx
fifos to support 7.1CH recording in TDM mode. Due to more no.
of root clock frequency values some of the bit offsets got
shifted up by one. Also I2S1 on previous Samsung platforms
uses v3 dai type but on Exynos7 it is upgraded to v5 with
slightly modified register offsets for supporting more no.of
RFS values. Due to the above changes, the driver has to be
modified to handle all versions of I2S controller. For this
I introduced a new structure to hold modified bit offsets and
masks which is passed as dai data.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/samsung/i2s-regs.h')
| -rw-r--r-- | sound/soc/samsung/i2s-regs.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/sound/soc/samsung/i2s-regs.h b/sound/soc/samsung/i2s-regs.h index 821a50231002..9170c311d66e 100644 --- a/sound/soc/samsung/i2s-regs.h +++ b/sound/soc/samsung/i2s-regs.h @@ -33,8 +33,9 @@ #define I2SLVL3ADDR 0x3c #define I2SSTR1 0x40 #define I2SVER 0x44 -#define I2SFIC2 0x48 +#define I2SFIC1 0x48 #define I2STDM 0x4c +#define I2SFSTA 0x50 #define CON_RSTCLR (1 << 31) #define CON_FRXOFSTATUS (1 << 26) @@ -93,8 +94,6 @@ #define MOD_BLC_24BIT (2 << 13) #define MOD_BLC_MASK (3 << 13) -#define MOD_IMS_SYSMUX (1 << 10) -#define MOD_SLAVE (1 << 11) #define MOD_TXONLY (0 << 8) #define MOD_RXONLY (1 << 8) #define MOD_TXRX (2 << 8) @@ -132,7 +131,10 @@ #define EXYNOS5420_MOD_BCLK_256FS 8 #define EXYNOS5420_MOD_BCLK_MASK 0xf -#define MOD_CDCLKCON (1 << 12) +#define EXYNOS7_MOD_RCLK_64FS 4 +#define EXYNOS7_MOD_RCLK_128FS 5 +#define EXYNOS7_MOD_RCLK_96FS 6 +#define EXYNOS7_MOD_RCLK_192FS 7 #define PSR_PSREN (1 << 15) |