diff options
| author | Axel Lin <axel.lin@gmail.com> | 2011-05-27 19:30:53 +0400 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-05-28 21:57:21 +0400 |
| commit | 74ab24af4fe165de5af01d0507250dd099f096b0 (patch) | |
| tree | d226912df3d2a532734396ed3ab169d25fbee922 /sound/soc/codecs | |
| parent | a5fe6be42e5cadac4c2aef2b3714cfa8fadb6092 (diff) | |
| download | linux-74ab24af4fe165de5af01d0507250dd099f096b0.tar.xz | |
ASoC: Remove redundant freq assignment for max98095->sysclk/max98088->sysclk
Current implementation set max98095->sysclk/max98088->sysclk to freq twice.
Set it once is enough, this patch removes the first assignment in case
we may set invalid clock frequency to max98095->sysclk/max98088->sysclk.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Peter Hsiang <peter.hsiang@maxim-ic.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs')
| -rw-r--r-- | sound/soc/codecs/max98088.c | 2 | ||||
| -rw-r--r-- | sound/soc/codecs/max98095.c | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c index bb58bdb49853..93255ff48b4f 100644 --- a/sound/soc/codecs/max98088.c +++ b/sound/soc/codecs/max98088.c @@ -1401,8 +1401,6 @@ static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, if (freq == max98088->sysclk) return 0; - max98088->sysclk = freq; /* remember current sysclk */ - /* Setup clocks for slave mode, and using the PLL * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) * 0x02 (when master clk is 20MHz to 30MHz).. diff --git a/sound/soc/codecs/max98095.c b/sound/soc/codecs/max98095.c index a6cc94e1750b..fe19677bf4b5 100644 --- a/sound/soc/codecs/max98095.c +++ b/sound/soc/codecs/max98095.c @@ -1517,8 +1517,6 @@ static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, if (freq == max98095->sysclk) return 0; - max98095->sysclk = freq; /* remember current sysclk */ - /* Setup clocks for slave mode, and using the PLL * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) * 0x02 (when master clk is 20MHz to 40MHz).. |