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| author | Stephen Boyd <sboyd@kernel.org> | 2023-10-31 00:12:20 +0300 | 
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-10-31 00:12:20 +0300 | 
| commit | 720e4a4a68670dfda638da236d374fc7a4be0a28 (patch) | |
| tree | 945ec0820c0ef91119ecbe7555dd9243ed173666 /scripts/mod/empty.c | |
| parent | d33050aec3f6b37294dc318e9cdb969ed5094a2d (diff) | |
| parent | c3f187461f090edffcb556d89a2726a522d69ae9 (diff) | |
| parent | 75357829cc8ef20808f38b6256fa167f36267c9f (diff) | |
| parent | 9e952929dfe22aa1566d930f363213e1ccfe004d (diff) | |
| parent | 2790e2a33aa9e0710354aaabce8ae1a92925348f (diff) | |
| download | linux-720e4a4a68670dfda638da236d374fc7a4be0a28.tar.xz | |
Merge branches 'clk-renesas', 'clk-kunit', 'clk-regmap' and 'clk-frac-divider' into clk-next
 - Make clk kunit tests work with lockdep
 - Fix clk gate kunit test for big-endian
 - Convert more than a handful of clk drivers to use regmap maple tree
 - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk
   implementation
* clk-renesas: (23 commits)
  clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2
  clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
  clk: renesas: Add minimal boot support for RZ/G3S SoC
  clk: renesas: rzg2l: Add divider clock for RZ/G3S
  clk: renesas: rzg2l: Refactor SD mux driver
  clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header
  clk: renesas: rzg2l: Add struct clk_hw_data
  clk: renesas: rzg2l: Add support for RZ/G3S PLL
  clk: renesas: rzg2l: Remove critical area
  clk: renesas: rzg2l: Fix computation formula
  clk: renesas: rzg2l: Trust value returned by hardware
  clk: renesas: rzg2l: Lock around writes to mux register
  clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
  clk: renesas: rcar-gen3: Extend SDnH divider table
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC
  clk: renesas: r8a7795: Constify r8a7795_*_clks
  clk: renesas: r9a06g032: Name anonymous structs
  clk: renesas: r9a06g032: Fix kerneldoc warning
  clk: renesas: rzg2l: Use u32 for flag and mux_flags
  clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
  ...
* clk-kunit:
  clk: Fix clk gate kunit test on big-endian CPUs
  clk: Parameterize clk_leaf_mux_set_rate_parent
  clk: Drive clk_leaf_mux_set_rate_parent test from clk_ops
* clk-regmap:
  clk: versaclock7: Convert to use maple tree register cache
  clk: versaclock5: Convert to use maple tree register cache
  clk: versaclock3: Convert to use maple tree register cache
  clk: versaclock3: Remove redundant _is_writeable()
  clk: si570: Convert to use maple tree register cache
  clk: si544: Convert to use maple tree register cache
  clk: si5351: Convert to use maple tree register cache
  clk: si5341: Convert to use maple tree register cache
  clk: si514: Convert to use maple tree register cache
  clk: cdce925: Convert to use maple tree register cache
* clk-frac-divider:
  clk: fractional-divider: tests: Add test suite for edge cases
  clk: fractional-divider: Improve approximation when zero based and export
