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| author | Pali Rohár <pali@kernel.org> | 2021-11-25 15:45:56 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2022-01-04 17:58:43 +0300 |
| commit | e42b85583719adb87ab88dc7bcd41b38011f7d11 (patch) | |
| tree | ea4fa8ca12294177ba9221785bee835186ddba02 /scripts/generate_rust_analyzer.py | |
| parent | 319e6046bd5a59e09c1a08fd6f6929df4ae9a1dc (diff) | |
| download | linux-e42b85583719adb87ab88dc7bcd41b38011f7d11.tar.xz | |
PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge
According to PCI specifications bits [0:2] of Command Register, this should
be by default disabled on reset. So explicitly disable these bits at early
beginning of driver initialization.
Also remove code which unconditionally enables all 3 bits and let kernel
code (via pci_set_master() function) to handle bus mastering of PCI Bridge
via emulated PCI_COMMAND on emulated bridge.
Adjust existing functions mvebu_pcie_handle_iobase_change() and
mvebu_pcie_handle_membase_change() to handle PCI_IO_BASE and PCI_MEM_BASE
registers correctly even when bus mastering on emulated bridge is disabled.
Link: https://lore.kernel.org/r/20211125124605.25915-7-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions