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| author | Vignesh Raghavendra <vigneshr@ti.com> | 2022-04-25 09:31:20 +0300 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2022-04-26 15:05:55 +0300 |
| commit | c7666240ec76422cb7546bd07cc8ae80dc0ccdd2 (patch) | |
| tree | 7d397df564b0eab77c7c96249f0758fe4d88ea42 /scripts/generate_rust_analyzer.py | |
| parent | 7a0587496a6233b9ffa8441573d38f8844751066 (diff) | |
| download | linux-c7666240ec76422cb7546bd07cc8ae80dc0ccdd2.tar.xz | |
drivers: mmc: sdhci_am654: Add the quirk to set TESTCD bit
The ARASAN MMC controller on Keystone 3 class of devices need the SDCD
line to be connected for proper functioning. Similar to the issue pointed
out in sdhci-of-arasan.c driver, commit 3794c542641f ("mmc:
sdhci-of-arasan: Set controller to test mode when no CD bit").
In cases where this can't be connected, add a quirk to force the
controller into test mode and set the TESTCD bit. Use the flag
"ti,fails-without-test-cd", to implement this above quirk when required.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20220425063120.10135-3-a-govindraju@ti.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions