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| author | Eric Huang <jinhuieric.huang@amd.com> | 2021-07-14 21:44:53 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-08-03 00:21:25 +0300 |
| commit | a50fe707803555f89ad878e3965445be0f70eb9f (patch) | |
| tree | 38ead57a342ed7434fde68f45dd4bd472b3389fa /scripts/generate_rust_analyzer.py | |
| parent | 3cd293a78a58c7172b338fd41b7b7a052db64955 (diff) | |
| download | linux-a50fe707803555f89ad878e3965445be0f70eb9f.tar.xz | |
drm/amdkfd: Only apply heavy-weight TLB flush on Aldebaran
It is to workaround HW bug on other Asics and based on
reverting two commits back:
drm/amdkfd: Add heavy-weight TLB flush after unmapping
drm/amdkfd: Add memory sync before TLB flush on unmap
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions