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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2019-03-25 12:39:46 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-05-01 17:50:13 +0300 |
| commit | 5bb04b19230c02cc1b450b029856cbe093e09908 (patch) | |
| tree | 0bc6058c786892ee08e1e6f55eb82b7687709634 /scripts/generate_rust_analyzer.py | |
| parent | 6b7330303a8186fb211357e6d379237fe9d2ece1 (diff) | |
| download | linux-5bb04b19230c02cc1b450b029856cbe093e09908.tar.xz | |
misc: pci_endpoint_test: Add support to test PCI EP in AM654x
TI's AM654x PCIe EP has a restriction that BAR_0 is mapped to
application registers. "PCIe Inbound Address Translation" section in
AM65x Sitara Processors TRM (SPRUID7 – April 2018) describes BAR0 as
reserved.
Configure pci_endpoint_test to use BAR_2 instead.
Also set alignment to 64K since "PCIe Subsystem Address Translation"
section in TRM indicates minimum ATU window size is 64K.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions