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| author | Thierry Reding <treding@nvidia.com> | 2015-04-08 18:06:08 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-08-13 14:47:16 +0300 |
| commit | 8ed5c0623272663783e052123fea02651464a0a5 (patch) | |
| tree | 54b8e1415d9187d5093a4669c7cf714553a1facc /scripts/gdb | |
| parent | 83a3c223cc5678c5ced554fa2819747fd53437c7 (diff) | |
| download | linux-8ed5c0623272663783e052123fea02651464a0a5.tar.xz | |
gpu: host1x: mipi: Fix clock lane register for DSI
Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'scripts/gdb')
0 files changed, 0 insertions, 0 deletions