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| author | Swapnil Jakhade <sjakhade@cadence.com> | 2021-12-23 09:01:29 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-12-27 14:05:09 +0300 |
| commit | fa10517211f72f9480677796b97cbe5a8f3a298f (patch) | |
| tree | db89745fbb7a5229ff7920841527120f7dacbc56 /scripts/gdb/linux/utils.py | |
| parent | 8c95e1722689f1b1e63a6206acba2b6200ed7864 (diff) | |
| download | linux-fa10517211f72f9480677796b97cbe5a8f3a298f.tar.xz | |
phy: cadence: Sierra: Add PHY PCS common register configurations
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-8-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions