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| author | Swapnil Jakhade <sjakhade@cadence.com> | 2021-12-23 09:01:32 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-12-27 14:05:09 +0300 |
| commit | 7a5ad9b4b98cd95f02ec12c895e80bc521fbf9ec (patch) | |
| tree | 55d97e785c13ad680ad237c7e414ad558dafa281 /scripts/gdb/linux/utils.py | |
| parent | 36ce416330da5b27d84af519f61e94b73596a297 (diff) | |
| download | linux-7a5ad9b4b98cd95f02ec12c895e80bc521fbf9ec.tar.xz | |
phy: cadence: Sierra: Update single link PCIe register configuration
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-11-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions