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| author | Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com> | 2024-09-09 11:25:04 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2024-09-12 06:53:43 +0300 |
| commit | 1f9c4eed9c115960b485fca42ad49c1a713dd099 (patch) | |
| tree | 8bd9e505c94929824cd11b5fc8089083cbd8a6da /scripts/gdb/linux/utils.py | |
| parent | 375d1e0278cca70ce801d52c6b95c7a3c00f249c (diff) | |
| download | linux-1f9c4eed9c115960b485fca42ad49c1a713dd099.tar.xz | |
net: ethernet: oa_tc6: implement software reset
Reset complete bit is set when the MAC-PHY reset completes and ready for
configuration. Additionally reset complete bit in the STS0 register has
to be written by one upon reset complete to clear the interrupt.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com>
Link: https://patch.msgid.link/20240909082514.262942-5-Parthiban.Veerasooran@microchip.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions