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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-02-05 19:56:40 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-03-06 09:40:36 +0300 |
| commit | e6f50b223da10de6bd70b8b9d217bd0c77ae5c13 (patch) | |
| tree | 9ccfde4a1ec87d07da58f50884536f4f85d4ea76 /scripts/gdb/linux/modules.py | |
| parent | bab86b948e8e1052a82c8723db717ae3d727f2fa (diff) | |
| download | linux-e6f50b223da10de6bd70b8b9d217bd0c77ae5c13.tar.xz | |
ARM: sun5i: Rename UART3 flow control pins
The UART3 pin group for the CTS and RTS signals doesn't follow our usual
pattern. Rename it so that it matches.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions