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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2015-11-05 21:50:20 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-11-18 13:22:34 +0300 |
| commit | c6297843829469571639f04d62292d1c75676b20 (patch) | |
| tree | 33ddc2f5ca0e28ea64a0b34621af5045da16be37 /scripts/gdb/linux/modules.py | |
| parent | d72f9d919a60e5096105237a72f046b7a20fb53f (diff) | |
| download | linux-c6297843829469571639f04d62292d1c75676b20.tar.xz | |
drm/i915: Make Sink crc calculation waiting for counter to reset.
According to VESA DP spec TEST_CRC_COUNT (Bits 3:0) at
TEST_SINK_MISC (00246h) is "Reset to 0 when TEST_SINK bit 0 = 0;
So let's give few vblanks so we are really sure that this counter
is really zeroed on the next sink_crc read.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions