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| author | Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2024-05-27 16:15:41 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-06-03 10:46:18 +0300 |
| commit | 7c8730df594e32d46d6728c07f89ea75c5e6a71d (patch) | |
| tree | da61e438325d88c1871128fe293f1ea98dd79da0 /scripts/gdb/linux/lists.py | |
| parent | babc0ea4e6813819ba55cefad8f68598a847e7e6 (diff) | |
| download | linux-7c8730df594e32d46d6728c07f89ea75c5e6a71d.tar.xz | |
clk: renesas: r8a779h0: Add CSI-2 clocks
Add the CSI40 and CSI41 module clocks, which are used by the CSI-2
interfaces on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240527131541.1676525-4-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions