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| author | Vidya Sagar <vidyas@nvidia.com> | 2022-07-21 17:20:46 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-07-23 01:14:56 +0300 |
| commit | 6646e99bcec627e866bc84365af37942c72b4b76 (patch) | |
| tree | f39842c22920dedb3e1a7bb11fc33af27d1e0dd1 /scripts/gdb/linux/lists.py | |
| parent | 997b99e3b386bde1d519d39f5276b10c67a8f172 (diff) | |
| download | linux-6646e99bcec627e866bc84365af37942c72b4b76.tar.xz | |
PCI: tegra194: Fix Root Port interrupt handling
As part of Root Port interrupt handling, level-0 register is read first and
based on the bits set in that, corresponding level-1 registers are read for
further interrupt processing. Since both these values are currently read
into the same 'val' variable, checking level-0 bits the second time around
is happening on the 'val' variable value of level-1 register contents
instead of freshly reading the level-0 value again.
Fix by using different variables to store level-0 and level-1 registers
contents.
Link: https://lore.kernel.org/r/20220721142052.25971-11-vidyas@nvidia.com
Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions