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| author | Shyam Sundar S K <Shyam-sundar.S-k@amd.com> | 2024-08-29 12:17:13 +0300 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2024-09-05 19:34:09 +0300 |
| commit | ced86959d28cc26bbfc5f2fd6e37407637c20e11 (patch) | |
| tree | 1c6b4bfa566f6a1294c0a5b9aac00104562a127f /rust/helpers/helpers.c | |
| parent | 46d4daa517e91a197ad253c1d81de29e8e2980be (diff) | |
| download | linux-ced86959d28cc26bbfc5f2fd6e37407637c20e11.tar.xz | |
i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold
The current driver sets the response buffer threshold value to 1
(N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD
I3C controller only generates interrupts when the response buffer
threshold value is set to 0 (1 DWORD).
Therefore, a quirk is added to set the response buffer threshold value
to 0.
Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20240829091713.736217-7-Shyam-sundar.S-k@amd.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'rust/helpers/helpers.c')
0 files changed, 0 insertions, 0 deletions