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authorBartosz Wawrzyniak <bwawrzyn@cisco.com>2024-10-03 15:34:02 +0300
committerVinod Koul <vkoul@kernel.org>2024-10-07 09:25:34 +0300
commit2d0f973b5f1c369671d0c59e103d15f4f6f775c9 (patch)
tree5dc0a7eda8609c3f29adb304e8f1f79eaef3b31c /rust/helpers/build_bug.c
parentcb4c7df596a9048a6025e96e62fe698f15ec1992 (diff)
downloadlinux-2d0f973b5f1c369671d0c59e103d15f4f6f775c9.tar.xz
phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control register
Fix the value of SIERRA_DEQ_OPENEYE_CTRL_PREG and add a definition for SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG. This fixes the SGMII single link register configuration. Fixes: 7a5ad9b4b98c ("phy: cadence: Sierra: Update single link PCIe register configuration") Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com> Link: https://lore.kernel.org/r/20241003123405.1101157-1-bwawrzyn@cisco.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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