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| author | Sergej Sawazki <sergej@taudac.com> | 2017-09-16 14:44:42 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-22 05:09:19 +0300 |
| commit | b26ff127c52c005ac4eb99ebff7bd17c240c2e89 (patch) | |
| tree | dac2abdb49523767791ac8b42b35bde65f4b562a /include/linux/fpga/fpga-mgr.h | |
| parent | 51279ef9f64cf7eb8b3f891a2b60fa1aa4938afc (diff) | |
| download | linux-b26ff127c52c005ac4eb99ebff7bd17c240c2e89.tar.xz | |
clk: si5351: Apply PLL soft reset before enabling the outputs
The "Si5351A/B/C Data Sheet" states to apply a PLL soft reset before
enabling the output clocks [1]. This is required to get a deterministic
phase relationship between the output clocks.
Without resetting the PLL, the phase relationship between the clocks is
unpredictable. Fix this by resetting the PLL in si5351_clkout_prepare().
References:
[1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf
Figure 12 ("I2C Programming Procedure")
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Sergej Sawazki <sergej@taudac.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/linux/fpga/fpga-mgr.h')
0 files changed, 0 insertions, 0 deletions