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| author | Dragos Bogdan <dragos.bogdan@analog.com> | 2019-05-16 10:04:43 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2019-05-21 08:06:05 +0300 |
| commit | 8add6cce98482da67e971addd7eae8f22f8e6c7a (patch) | |
| tree | fb18916dad4ef0fdf4a1584bef234c0b1de8c947 /include/linux/fpga/fpga-mgr.h | |
| parent | e40543931fe34d7808bf87398a0daca44c919d25 (diff) | |
| download | linux-8add6cce98482da67e971addd7eae8f22f8e6c7a.tar.xz | |
dmaengine: axi-dmac: Add support for interleaved cyclic transfers
The DMAC HDL core supports interleaved & cyclic transfers.
An example use-case for this mode is when the controller is used as a
video DMA.
This change sets the `cyclic` field to true, so that when the IRQ comes and
the `axi_dmac_transfer_done()` callback is called (from the interrupt
handler) the proper `vchan_cyclic_callback()` is called. This way the
DMAEngine framework will process data correctly for interleaved + cyclic
transfers.
This doesn't fix anything. It's an enhancement to the driver.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include/linux/fpga/fpga-mgr.h')
0 files changed, 0 insertions, 0 deletions