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authorSuresh Siddha <suresh.b.siddha@intel.com>2008-07-10 22:16:52 +0400
committerIngo Molnar <mingo@elte.hu>2008-07-12 10:45:01 +0400
commit13c88fb58d0112d47f7839f24a755715c6218822 (patch)
tree32fb7ab893b6bcb687ad31bd841acf311a113252 /include/asm-x86/apicdef.h
parent1cb11583a6c4ceda7426eb36f7bf0419da8dfbc2 (diff)
downloadlinux-13c88fb58d0112d47f7839f24a755715c6218822.tar.xz
x64, x2apic/intr-remap: x2apic ops for x2apic mode support
x2apic ops for x2apic mode support. This uses MSR interface and differs slightly from the xapic register layout. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/apicdef.h')
-rw-r--r--include/asm-x86/apicdef.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-x86/apicdef.h b/include/asm-x86/apicdef.h
index 6b9008c78731..bcae297b30b2 100644
--- a/include/asm-x86/apicdef.h
+++ b/include/asm-x86/apicdef.h
@@ -105,6 +105,7 @@
#define APIC_TMICT 0x380
#define APIC_TMCCT 0x390
#define APIC_TDCR 0x3E0
+#define APIC_SELF_IPI 0x3F0
#define APIC_TDR_DIV_TMBASE (1 << 2)
#define APIC_TDR_DIV_1 0xB
#define APIC_TDR_DIV_2 0x0
@@ -128,6 +129,8 @@
#define APIC_EILVT3 0x530
#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
+#define APIC_BASE_MSR 0x800
+#define X2APIC_ENABLE (1UL << 10)
#ifdef CONFIG_X86_32
# define MAX_IO_APICS 64