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authorRalf Baechle <ralf@linux-mips.org>2006-02-01 18:29:21 +0300
committerRalf Baechle <ralf@linux-mips.org>2006-02-07 16:30:25 +0300
commit1e32ceeca25ea30cabce137fac7e2f58fe8847db (patch)
tree603e9388af3bf1043d0039198bbb236d6b4a41dd /include/asm-mips/byteorder.h
parent7e5b24ac759176e55c8a535fff6533366168cbe9 (diff)
downloadlinux-1e32ceeca25ea30cabce137fac7e2f58fe8847db.tar.xz
[MIPS] MIPS R2 optimized endianess swapping.
From Franck Bui-Huu <vagabon.xyz@gmail.com> with modifications by me. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/byteorder.h')
-rw-r--r--include/asm-mips/byteorder.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index d1fe9e5c62e4..584f8128fffd 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -8,10 +8,39 @@
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
+#include <linux/config.h>
+#include <linux/compiler.h>
#include <asm/types.h>
#ifdef __GNUC__
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+ __asm__(
+ " wsbh %0, %1 \n"
+ : "=r" (x)
+ : "r" (x));
+
+ return x;
+}
+#define __arch__swab16(x) ___arch__swab16(x)
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+ __asm__(
+ " wsbh %0, %1 \n"
+ " rotr %0, %0, 16 \n"
+ : "=r" (x)
+ : "r" (x));
+
+ return x;
+}
+#define __arch__swab32(x) ___arch__swab32(x)
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__