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| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2018-03-02 00:34:35 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-03-02 10:45:22 +0300 |
| commit | e420ccd66d36e4ac2035620286495ce13a40b7f7 (patch) | |
| tree | 7db46e447eabb74fd05b0a3df215fff3fd027b74 /drivers | |
| parent | e679f4a13f0fd1da4ef5b9c59c78404cd421c61b (diff) | |
| download | linux-e420ccd66d36e4ac2035620286495ce13a40b7f7.tar.xz | |
drm/sun4i: Fix polarity configuration for DW HDMI PHY
Current polarity configuration code is cleary wrong since it compares
same flag two times. However, even if flag name is fixed, it won't work
well for resolutions which have one polarity positive and another
negative.
Fix that by properly set each bit according to each polarity. Since
those two bits are not described in any documentation, relationships
were obtained by experimentation.
Fixes: b7c7436a5ff0 ("drm/sun4i: Implement A83T HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180301213442.16677-10-jernej.skrabec@siol.net
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index e5bfcdd43ec9..9d2f11ca3538 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c @@ -10,7 +10,8 @@ #define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000 #define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0) #define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8) -#define SUN8I_HDMI_PHY_DBG_CTRL_POL(val) (val << 8) +#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8) +#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9) #define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16) #define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16) @@ -35,14 +36,14 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data; u32 val = 0; - if ((mode->flags & DRM_MODE_FLAG_NHSYNC) && - (mode->flags & DRM_MODE_FLAG_NHSYNC)) { - val = 0x03; - } + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC; + + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC; regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, - SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, - SUN8I_HDMI_PHY_DBG_CTRL_POL(val)); + SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val); regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, |