diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-05-23 03:02:13 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-05-23 03:02:13 +0400 |
| commit | 5d4e2d08e7fdf7339f84a1c670d296a77e02f881 (patch) | |
| tree | 1c419660defa56191091dfdf50fdb57a72009173 /drivers | |
| parent | fb2123fad3b499f0898835b19dbb93b18d27ee98 (diff) | |
| parent | 94ca629e40eb7e997be21d8065c25e4f3797b03f (diff) | |
| download | linux-5d4e2d08e7fdf7339f84a1c670d296a77e02f881.tar.xz | |
Merge tag 'driver-core-3.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core
Pull driver core updates from Greg Kroah-Hartman:
"Here's the driver core, and other driver subsystems, pull request for
the 3.5-rc1 merge window.
Outside of a few minor driver core changes, we ended up with the
following different subsystem and core changes as well, due to
interdependancies on the driver core:
- hyperv driver updates
- drivers/memory being created and some drivers moved into it
- extcon driver subsystem created out of the old Android staging
switch driver code
- dynamic debug updates
- printk rework, and /dev/kmsg changes
All of this has been tested in the linux-next releases for a few weeks
with no reported problems.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>"
Fix up conflicts in drivers/extcon/extcon-max8997.c where git noticed
that a patch to the deleted drivers/misc/max8997-muic.c driver needs to
be applied to this one.
* tag 'driver-core-3.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (90 commits)
uio_pdrv_genirq: get irq through platform resource if not set otherwise
memory: tegra{20,30}-mc: Remove empty *_remove()
printk() - isolate KERN_CONT users from ordinary complete lines
sysfs: get rid of some lockdep false positives
Drivers: hv: util: Properly handle version negotiations.
Drivers: hv: Get rid of an unnecessary check in vmbus_prep_negotiate_resp()
memory: tegra{20,30}-mc: Use dev_err_ratelimited()
driver core: Add dev_*_ratelimited() family
Driver Core: don't oops with unregistered driver in driver_find_device()
printk() - restore prefix/timestamp printing for multi-newline strings
printk: add stub for prepend_timestamp()
ARM: tegra30: Make MC optional in Kconfig
ARM: tegra20: Make MC optional in Kconfig
ARM: tegra30: MC: Remove unnecessary BUG*()
ARM: tegra20: MC: Remove unnecessary BUG*()
printk: correctly align __log_buf
ARM: tegra30: Add Tegra Memory Controller(MC) driver
ARM: tegra20: Add Tegra Memory Controller(MC) driver
printk() - restore timestamp printing at console output
printk() - do not merge continuation lines of different threads
...
Diffstat (limited to 'drivers')
43 files changed, 4322 insertions, 625 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig index d236aef7e59f..63b81826cb55 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -140,4 +140,8 @@ source "drivers/virt/Kconfig" source "drivers/devfreq/Kconfig" +source "drivers/extcon/Kconfig" + +source "drivers/memory/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 95952c82bf16..265b506a15be 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -134,3 +134,5 @@ obj-$(CONFIG_VIRT_DRIVERS) += virt/ obj-$(CONFIG_HYPERV) += hv/ obj-$(CONFIG_PM_DEVFREQ) += devfreq/ +obj-$(CONFIG_EXTCON) += extcon/ +obj-$(CONFIG_MEMORY) += memory/ diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c index 4a29763b8eb4..a12808259dfb 100644 --- a/drivers/acpi/pci_link.c +++ b/drivers/acpi/pci_link.c @@ -720,21 +720,21 @@ static int acpi_pci_link_add(struct acpi_device *device) acpi_device_bid(device)); for (i = 0; i < link->irq.possible_count; i++) { if (link->irq.active == link->irq.possible[i]) { - printk(" *%d", link->irq.possible[i]); + printk(KERN_CONT " *%d", link->irq.possible[i]); found = 1; } else - printk(" %d", link->irq.possible[i]); + printk(KERN_CONT " %d", link->irq.possible[i]); } - printk(")"); + printk(KERN_CONT ")"); if (!found) - printk(" *%d", link->irq.active); + printk(KERN_CONT " *%d", link->irq.active); if (!link->device->status.enabled) - printk(", disabled."); + printk(KERN_CONT ", disabled."); - printk("\n"); + printk(KERN_CONT "\n"); list_add_tail(&link->list, &acpi_link_list); diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c index eb6fd233764b..06527c526618 100644 --- a/drivers/acpi/sleep.c +++ b/drivers/acpi/sleep.c @@ -887,7 +887,7 @@ int __init acpi_sleep_init(void) status = acpi_get_sleep_type_data(i, &type_a, &type_b); if (ACPI_SUCCESS(status)) { sleep_states[i] = 1; - printk(" S%d", i); + printk(KERN_CONT " S%d", i); } } @@ -901,7 +901,7 @@ int __init acpi_sleep_init(void) hibernation_set_ops(old_suspend_ordering ? &acpi_hibernation_ops_old : &acpi_hibernation_ops); sleep_states[ACPI_STATE_S4] = 1; - printk(" S4"); + printk(KERN_CONT " S4"); if (!nosigcheck) { acpi_get_table(ACPI_SIG_FACS, 1, (struct acpi_table_header **)&facs); @@ -914,11 +914,11 @@ int __init acpi_sleep_init(void) status = acpi_get_sleep_type_data(ACPI_STATE_S5, &type_a, &type_b); if (ACPI_SUCCESS(status)) { sleep_states[ACPI_STATE_S5] = 1; - printk(" S5"); + printk(KERN_CONT " S5"); pm_power_off_prepare = acpi_power_off_prepare; pm_power_off = acpi_power_off; } - printk(")\n"); + printk(KERN_CONT ")\n"); /* * Register the tts_notifier to reboot notifier list so that the _TTS * object can also be evaluated when the system enters S5. diff --git a/drivers/base/bus.c b/drivers/base/bus.c index 26a06b801b5b..2bcef657a60c 100644 --- a/drivers/base/bus.c +++ b/drivers/base/bus.c @@ -21,8 +21,7 @@ #include "power/power.h" /* /sys/devices/system */ -/* FIXME: make static after drivers/base/sys.c is deleted */ -struct kset *system_kset; +static struct kset *system_kset; #define to_bus_attr(_attr) container_of(_attr, struct bus_attribute, attr) diff --git a/drivers/base/core.c b/drivers/base/core.c index e28ce9898af4..346be8b78b24 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -25,6 +25,7 @@ #include <linux/mutex.h> #include <linux/async.h> #include <linux/pm_runtime.h> +#include <linux/netdevice.h> #include "base.h" #include "power/power.h" @@ -65,7 +66,7 @@ static inline int device_is_not_partition(struct device *dev) * @dev: struct device to get the name of * * Will return the device's driver's name if it is bound to a device. If - * the device is not bound to a device, it will return the name of the bus + * the device is not bound to a driver, it will return the name of the bus * it is attached to. If it is not attached to a bus either, an empty * string will be returned. */ @@ -878,8 +879,8 @@ EXPORT_SYMBOL_GPL(dev_set_name); * to NULL prevents an entry from being created. class->dev_kobj must * be set (or cleared) before any devices are registered to the class * otherwise device_create_sys_dev_entry() and - * device_remove_sys_dev_entry() will disagree about the the presence - * of the link. + * device_remove_sys_dev_entry() will disagree about the presence of + * the link. */ static struct kobject *device_to_dev_kobj(struct device *dev) { @@ -1843,15 +1844,60 @@ void device_shutdown(void) */ #ifdef CONFIG_PRINTK - int __dev_printk(const char *level, const struct device *dev, struct va_format *vaf) { + char dict[128]; + size_t dictlen = 0; + const char *subsys; + if (!dev) return printk("%s(NULL device *): %pV", level, vaf); - return printk("%s%s %s: %pV", - level, dev_driver_string(dev), dev_name(dev), vaf); + if (dev->class) + subsys = dev->class->name; + else if (dev->bus) + subsys = dev->bus->name; + else + goto skip; + + dictlen += snprintf(dict + dictlen, sizeof(dict) - dictlen, + "SUBSYSTEM=%s", subsys); + + /* + * Add device identifier DEVICE=: + * b12:8 block dev_t + * c127:3 char dev_t + * n8 netdev ifindex + * +sound:card0 subsystem:devname + */ + if (MAJOR(dev->devt)) { + char c; + + if (strcmp(subsys, "block") == 0) + c = 'b'; + else + c = 'c'; + dictlen++; + dictlen += snprintf(dict + dictlen, sizeof(dict) - dictlen, + "DEVICE=%c%u:%u", + c, MAJOR(dev->devt), MINOR(dev->devt)); + } else if (strcmp(subsys, "net") == 0) { + struct net_device *net = to_net_dev(dev); + + dictlen++; + dictlen += snprintf(dict + dictlen, sizeof(dict) - dictlen, + "DEVICE=n%u", net->ifindex); + } else { + dictlen++; + dictlen += snprintf(dict + dictlen, sizeof(dict) - dictlen, + "DEVICE=+%s:%s", subsys, dev_name(dev)); + } +skip: + return printk_emit(0, level[1] - '0', + dictlen ? dict : NULL, dictlen, + "%s %s: %pV", + dev_driver_string(dev), dev_name(dev), vaf); } EXPORT_SYMBOL(__dev_printk); diff --git a/drivers/base/devres.c b/drivers/base/devres.c index 524bf96c289f..2360adb7a58f 100644 --- a/drivers/base/devres.c +++ b/drivers/base/devres.c @@ -309,6 +309,10 @@ EXPORT_SYMBOL_GPL(devres_remove); * which @match returns 1. If @match is NULL, it's considered to * match all. If found, the resource is removed atomically and freed. * + * Note that the release function for the resource will not be called, + * only the devres-allocated data will be freed. The caller becomes + * responsible for freeing any other data. + * * RETURNS: * 0 if devres is found and freed, -ENOENT if not found. */ @@ -326,6 +330,37 @@ int devres_destroy(struct device *dev, dr_release_t release, } EXPORT_SYMBOL_GPL(devres_destroy); + +/** + * devres_release - Find a device resource and destroy it, calling release + * @dev: Device to find resource from + * @release: Look for resources associated with this release function + * @match: Match function (optional) + * @match_data: Data for the match function + * + * Find the latest devres of @dev associated with @release and for + * which @match returns 1. If @match is NULL, it's considered to + * match all. If found, the resource is removed atomically, the + * release function called and the resource freed. + * + * RETURNS: + * 0 if devres is found and freed, -ENOENT if not found. + */ +int devres_release(struct device *dev, dr_release_t release, + dr_match_t match, void *match_data) +{ + void *res; + + res = devres_remove(dev, release, match, match_data); + if (unlikely(!res)) + return -ENOENT; + + (*release)(dev, res); + devres_free(res); + return 0; +} +EXPORT_SYMBOL_GPL(devres_release); + static int remove_nodes(struct device *dev, struct list_head *first, struct list_head *end, struct list_head *todo) diff --git a/drivers/base/devtmpfs.c b/drivers/base/devtmpfs.c index 8493536ea55b..765c3a28077a 100644 --- a/drivers/base/devtmpfs.c +++ b/drivers/base/devtmpfs.c @@ -7,9 +7,9 @@ * devtmpfs, a tmpfs-based filesystem is created. Every driver-core * device which requests a device node, will add a node in this * filesystem. - * By default, all devices are named after the the name of the - * device, owned by root and have a default mode of 0600. Subsystems - * can overwrite the default setting if needed. + * By default, all devices are named after the name of the device, + * owned by root and have a default mode of 0600. Subsystems can + * overwrite the default setting if needed. */ #include <linux/kernel.h> diff --git a/drivers/base/dma-buf.c b/drivers/base/dma-buf.c index 07cbbc6fddb4..05c64c11bad2 100644 --- a/drivers/base/dma-buf.c +++ b/drivers/base/dma-buf.c @@ -293,7 +293,7 @@ EXPORT_SYMBOL_GPL(dma_buf_unmap_attachment); * cpu in the kernel context. Calls begin_cpu_access to allow exporter-specific * preparations. Coherency is only guaranteed in the specified range for the * specified access direction. - * @dma_buf: [in] buffer to prepare cpu access for. + * @dmabuf: [in] buffer to prepare cpu access for. * @start: [in] start of range for cpu access. * @len: [in] length of range for cpu access. * @direction: [in] length of range for cpu access. @@ -320,7 +320,7 @@ EXPORT_SYMBOL_GPL(dma_buf_begin_cpu_access); * cpu in the kernel context. Calls end_cpu_access to allow exporter-specific * actions. Coherency is only guaranteed in the specified range for the * specified access direction. - * @dma_buf: [in] buffer to complete cpu access for. + * @dmabuf: [in] buffer to complete cpu access for. * @start: [in] start of range for cpu access. * @len: [in] length of range for cpu access. * @direction: [in] length of range for cpu access. @@ -340,7 +340,7 @@ EXPORT_SYMBOL_GPL(dma_buf_end_cpu_access); /** * dma_buf_kmap_atomic - Map a page of the buffer object into kernel address * space. The same restrictions as for kmap_atomic and friends apply. - * @dma_buf: [in] buffer to map page from. + * @dmabuf: [in] buffer to map page from. * @page_num: [in] page in PAGE_SIZE units to map. * * This call must always succeed, any necessary preparations that might fail @@ -356,7 +356,7 @@ EXPORT_SYMBOL_GPL(dma_buf_kmap_atomic); /** * dma_buf_kunmap_atomic - Unmap a page obtained by dma_buf_kmap_atomic. - * @dma_buf: [in] buffer to unmap page from. + * @dmabuf: [in] buffer to unmap page from. * @page_num: [in] page in PAGE_SIZE units to unmap. * @vaddr: [in] kernel space pointer obtained from dma_buf_kmap_atomic. * @@ -375,7 +375,7 @@ EXPORT_SYMBOL_GPL(dma_buf_kunmap_atomic); /** * dma_buf_kmap - Map a page of the buffer object into kernel address space. The * same restrictions as for kmap and friends apply. - * @dma_buf: [in] buffer to map page from. + * @dmabuf: [in] buffer to map page from. * @page_num: [in] page in PAGE_SIZE units to map. * * This call must always succeed, any necessary preparations that might fail @@ -391,7 +391,7 @@ EXPORT_SYMBOL_GPL(dma_buf_kmap); /** * dma_buf_kunmap - Unmap a page obtained by dma_buf_kmap. - * @dma_buf: [in] buffer to unmap page from. + * @dmabuf: [in] buffer to unmap page from. * @page_num: [in] page in PAGE_SIZE units to unmap. * @vaddr: [in] kernel space pointer obtained from dma_buf_kmap. * diff --git a/drivers/base/driver.c b/drivers/base/driver.c index 3ec3896c83a6..207c27ddf828 100644 --- a/drivers/base/driver.c +++ b/drivers/base/driver.c @@ -80,7 +80,7 @@ struct device *driver_find_device(struct device_driver *drv, struct klist_iter i; struct device *dev; - if (!drv) + if (!drv || !drv->p) return NULL; klist_iter_init_node(&drv->p->klist_devices, &i, diff --git a/drivers/char/mem.c b/drivers/char/mem.c index d6e9d081c8b1..67c3371723cc 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -807,44 +807,6 @@ static const struct file_operations oldmem_fops = { }; #endif -static ssize_t kmsg_writev(struct kiocb *iocb, const struct iovec *iv, - unsigned long count, loff_t pos) -{ - char *line, *p; - int i; - ssize_t ret = -EFAULT; - size_t len = iov_length(iv, count); - - line = kmalloc(len + 1, GFP_KERNEL); - if (line == NULL) - return -ENOMEM; - - /* - * copy all vectors into a single string, to ensure we do - * not interleave our log line with other printk calls - */ - p = line; - for (i = 0; i < count; i++) { - if (copy_from_user(p, iv[i].iov_base, iv[i].iov_len)) - goto out; - p += iv[i].iov_len; - } - p[0] = '\0'; - - ret = printk("%s", line); - /* printk can add a prefix */ - if (ret > len) - ret = len; -out: - kfree(line); - return ret; -} - -static const struct file_operations kmsg_fops = { - .aio_write = kmsg_writev, - .llseek = noop_llseek, -}; - static const struct memdev { const char *name; umode_t mode; @@ -863,7 +825,9 @@ static const struct memdev { [7] = { "full", 0666, &full_fops, NULL }, [8] = { "random", 0666, &random_fops, NULL }, [9] = { "urandom", 0666, &urandom_fops, NULL }, - [11] = { "kmsg", 0, &kmsg_fops, NULL }, +#ifdef CONFIG_PRINTK + [11] = { "kmsg", 0644, &kmsg_fops, NULL }, +#endif #ifdef CONFIG_CRASH_DUMP [12] = { "oldmem", 0, &oldmem_fops, NULL }, #endif diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig new file mode 100644 index 000000000000..29c5cf852efc --- /dev/null +++ b/drivers/extcon/Kconfig @@ -0,0 +1,32 @@ +menuconfig EXTCON + tristate "External Connector Class (extcon) support" + help + Say Y here to enable external connector class (extcon) support. + This allows monitoring external connectors by userspace + via sysfs and uevent and supports external connectors with + multiple states; i.e., an extcon that may have multiple + cables attached. For example, an external connector of a device + may be used to connect an HDMI cable and a AC adaptor, and to + host USB ports. Many of 30-pin connectors including PDMI are + also good examples. + +if EXTCON + +comment "Extcon Device Drivers" + +config EXTCON_GPIO + tristate "GPIO extcon support" + depends on GENERIC_GPIO + help + Say Y here to enable GPIO based extcon support. Note that GPIO + extcon supports single state per extcon instance. + +config EXTCON_MAX8997 + tristate "MAX8997 EXTCON Support" + depends on MFD_MAX8997 + help + If you say yes here you get support for the MUIC device of + Maxim MAX8997 PMIC. The MAX8997 MUIC is a USB port accessory + detector and switch. + +endif # MULTISTATE_SWITCH diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile new file mode 100644 index 000000000000..86020bdb6da0 --- /dev/null +++ b/drivers/extcon/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for external connector class (extcon) devices +# + +obj-$(CONFIG_EXTCON) += extcon_class.o +obj-$(CONFIG_EXTCON_GPIO) += extcon_gpio.o +obj-$(CONFIG_EXTCON_MAX8997) += extcon-max8997.o diff --git a/drivers/misc/max8997-muic.c b/drivers/extcon/extcon-max8997.c index 2e7df9c56491..23416e443765 100644 --- a/drivers/misc/max8997-muic.c +++ b/drivers/extcon/extcon-max8997.c @@ -1,7 +1,7 @@ /* - * max8997-muic.c - MAX8997 muic driver for the Maxim 8997 + * extcon-max8997.c - MAX8997 extcon driver to support MAX8997 MUIC * - * Copyright (C) 2011 Samsung Electrnoics + * Copyright (C) 2012 Samsung Electrnoics * Donggeun Kim <dg77.kim@samsung.com> * * This program is free software; you can redistribute it and/or modify @@ -13,11 +13,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ #include <linux/kernel.h> @@ -30,6 +25,9 @@ #include <linux/kobject.h> #include <linux/mfd/max8997.h> #include <linux/mfd/max8997-private.h> +#include <linux/extcon.h> + +#define DEV_NAME "max8997-muic" /* MAX8997-MUIC STATUS1 register */ #define STATUS1_ADC_SHIFT 0 @@ -95,7 +93,6 @@ static struct max8997_muic_irq muic_irqs[] = { struct max8997_muic_info { struct device *dev; - struct max8997_dev *iodev; struct i2c_client *muic; struct max8997_muic_platform_data *muic_pdata; @@ -106,12 +103,28 @@ struct max8997_muic_info { int pre_adc; struct mutex mutex; + + struct extcon_dev *edev; +}; + +const char *max8997_extcon_cable[] = { + [0] = "USB", + [1] = "USB-Host", + [2] = "TA", + [3] = "Fast-charger", + [4] = "Slow-charger", + [5] = "Charge-downstream", + [6] = "MHL", + [7] = "Dock-desk", + [7] = "Dock-card", + [8] = "JIG", + + NULL, }; static int max8997_muic_handle_usb(struct max8997_muic_info *info, enum max8997_muic_usb_type usb_type, bool attached) { - struct max8997_muic_platform_data *mdata = info->muic_pdata; int ret = 0; if (usb_type == MAX8997_USB_HOST) { @@ -125,25 +138,25 @@ static int max8997_muic_handle_usb(struct max8997_muic_info *info, } } - if (mdata->usb_callback) - mdata->usb_callback(usb_type, attached); + switch (usb_type) { + case MAX8997_USB_HOST: + extcon_set_cable_state(info->edev, "USB-Host", attached); + break; + case MAX8997_USB_DEVICE: + extcon_set_cable_state(info->edev, "USB", attached); + break; + default: + ret = -EINVAL; + break; + } + out: return ret; } -static void max8997_muic_handle_mhl(struct max8997_muic_info *info, - bool attached) -{ - struct max8997_muic_platform_data *mdata = info->muic_pdata; - - if (mdata->mhl_callback) - mdata->mhl_callback(attached); -} - static int max8997_muic_handle_dock(struct max8997_muic_info *info, int adc, bool attached) { - struct max8997_muic_platform_data *mdata = info->muic_pdata; int ret = 0; /* switch to AUDIO */ @@ -157,14 +170,13 @@ static int max8997_muic_handle_dock(struct max8997_muic_info *info, switch (adc) { case MAX8997_ADC_DESKDOCK: - if (mdata->deskdock_callback) - mdata->deskdock_callback(attached); + extcon_set_cable_state(info->edev, "Dock-desk", attached); break; case MAX8997_ADC_CARDOCK: - if (mdata->cardock_callback) - mdata->cardock_callback(attached); + extcon_set_cable_state(info->edev, "Dock-card", attached); break; default: + ret = -EINVAL; break; } out: @@ -174,7 +186,6 @@ out: static int max8997_muic_handle_jig_uart(struct max8997_muic_info *info, bool attached) { - struct max8997_muic_platform_data *mdata = info->muic_pdata; int ret = 0; /* switch to UART */ @@ -186,8 +197,7 @@ static int max8997_muic_handle_jig_uart(struct max8997_muic_info *info, goto out; } - if (mdata->uart_callback) - mdata->uart_callback(attached); + extcon_set_cable_state(info->edev, "JIG", attached); out: return ret; } @@ -201,7 +211,7 @@ static int max8997_muic_handle_adc_detach(struct max8997_muic_info *info) ret = max8997_muic_handle_usb(info, MAX8997_USB_HOST, false); break; case MAX8997_ADC_MHL: - max8997_muic_handle_mhl(info, false); + extcon_set_cable_state(info->edev, "MHL", false); break; case MAX8997_ADC_JIG_USB_1: case MAX8997_ADC_JIG_USB_2: @@ -230,7 +240,7 @@ static int max8997_muic_handle_adc(struct max8997_muic_info *info, int adc) ret = max8997_muic_handle_usb(info, MAX8997_USB_HOST, true); break; case MAX8997_ADC_MHL: - max8997_muic_handle_mhl(info, true); + extcon_set_cable_state(info->edev, "MHL", true); break; case MAX8997_ADC_JIG_USB_1: case MAX8997_ADC_JIG_USB_2: @@ -247,10 +257,40 @@ static int max8997_muic_handle_adc(struct max8997_muic_info *info, int adc) ret = max8997_muic_handle_adc_detach(info); break; default: - break; + ret = -EINVAL; + goto out; } info->pre_adc = adc; +out: + return ret; +} + +static int max8997_muic_handle_charger_type_detach( + struct max8997_muic_info *info) +{ + int ret = 0; + + switch (info->pre_charger_type) { + case MAX8997_CHARGER_TYPE_USB: + extcon_set_cable_state(info->edev, "USB", false); + break; + case MAX8997_CHARGER_TYPE_DOWNSTREAM_PORT: + extcon_set_cable_state(info->edev, "Charge-downstream", false); + break; + case MAX8997_CHARGER_TYPE_DEDICATED_CHG: + extcon_set_cable_state(info->edev, "TA", false); + break; + case MAX8997_CHARGER_TYPE_500MA: + extcon_set_cable_state(info->edev, "Slow-charger", false); + break; + case MAX8997_CHARGER_TYPE_1A: + extcon_set_cable_state(info->edev, "Fast-charger", false); + break; + default: + ret = -EINVAL; + break; + } return ret; } @@ -258,7 +298,6 @@ static int max8997_muic_handle_adc(struct max8997_muic_info *info, int adc) static int max8997_muic_handle_charger_type(struct max8997_muic_info *info, enum max8997_muic_charger_type charger_type) { - struct max8997_muic_platform_data *mdata = info->muic_pdata; u8 adc; int ret; @@ -270,30 +309,29 @@ static int max8997_muic_handle_charger_type(struct max8997_muic_info *info, switch (charger_type) { case MAX8997_CHARGER_TYPE_NONE: - if (mdata->charger_callback) - mdata->charger_callback(false, charger_type); - if (info->pre_charger_type == MAX8997_CHARGER_TYPE_USB) { - max8997_muic_handle_usb(info, - MAX8997_USB_DEVICE, false); - } + ret = max8997_muic_handle_charger_type_detach(info); break; case MAX8997_CHARGER_TYPE_USB: if ((adc & STATUS1_ADC_MASK) == MAX8997_ADC_OPEN) { max8997_muic_handle_usb(info, MAX8997_USB_DEVICE, true); } - if (mdata->charger_callback) - mdata->charger_callback(true, charger_type); break; case MAX8997_CHARGER_TYPE_DOWNSTREAM_PORT: + extcon_set_cable_state(info->edev, "Charge-downstream", true); + break; case MAX8997_CHARGER_TYPE_DEDICATED_CHG: + extcon_set_cable_state(info->edev, "TA", true); + break; case MAX8997_CHARGER_TYPE_500MA: + extcon_set_cable_state(info->edev, "Slow-charger", true); + break; case MAX8997_CHARGER_TYPE_1A: - if (mdata->charger_callback) - mdata->charger_callback(true, charger_type); + extcon_set_cable_state(info->edev, "Fast-charger", true); break; default: - break; + ret = -EINVAL; + goto out; } info->pre_charger_type = charger_type; @@ -305,18 +343,17 @@ static void max8997_muic_irq_work(struct work_struct *work) { struct max8997_muic_info *info = container_of(work, struct max8997_muic_info, irq_work); - struct max8997_platform_data *pdata = - dev_get_platdata(info->iodev->dev); - u8 status[3]; + struct max8997_dev *max8997 = i2c_get_clientdata(info->muic); + u8 status[2]; u8 adc, chg_type; - int irq_type = info->irq - pdata->irq_base; + int irq_type = info->irq - max8997->irq_base; int ret; mutex_lock(&info->mutex); ret = max8997_bulk_read(info->muic, MAX8997_MUIC_REG_STATUS1, - 3, status); + 2, status); if (ret) { dev_err(info->dev, "failed to read muic register\n"); mutex_unlock(&info->mutex); @@ -340,8 +377,8 @@ static void max8997_muic_irq_work(struct work_struct *work) max8997_muic_handle_charger_type(info, chg_type); break; default: - dev_info(info->dev, "misc interrupt: %s occurred\n", - muic_irqs[irq_type].name); + dev_info(info->dev, "misc interrupt: irq %d occurred\n", + irq_type); break; } @@ -387,21 +424,10 @@ static void max8997_muic_detect_dev(struct max8997_muic_info *info) max8997_muic_handle_charger_type(info, chg_type); } -static void max8997_initialize_device(struct max8997_muic_info *info) -{ - struct max8997_muic_platform_data *mdata = info->muic_pdata; - int i; - - for (i = 0; i < mdata->num_init_data; i++) { - max8997_write_reg(info->muic, mdata->init_data[i].addr, - mdata->init_data[i].data); - } -} - static int __devinit max8997_muic_probe(struct platform_device *pdev) { - struct max8997_dev *iodev = dev_get_drvdata(pdev->dev.parent); - struct max8997_platform_data *pdata = dev_get_platdata(iodev->dev); + struct max8997_dev *max8997 = dev_get_drvdata(pdev->dev.parent); + struct max8997_platform_data *pdata = dev_get_platdata(max8997->dev); struct max8997_muic_info *info; int ret, i; @@ -412,16 +438,8 @@ static int __devinit max8997_muic_probe(struct platform_device *pdev) goto err_kfree; } - if (!pdata->muic_pdata) { - dev_err(&pdev->dev, "failed to get platform_data\n"); - ret = -EINVAL; - goto err_pdata; - } - info->muic_pdata = pdata->muic_pdata; - info->dev = &pdev->dev; - info->iodev = iodev; - info->muic = iodev->muic; + info->muic = max8997->muic; platform_set_drvdata(pdev, info); mutex_init(&info->mutex); @@ -444,18 +462,41 @@ static int __devinit max8997_muic_probe(struct platform_device *pdev) } } + /* External connector */ + info->edev = kzalloc(sizeof(struct extcon_dev), GFP_KERNEL); + if (!info->edev) { + dev_err(&pdev->dev, "failed to allocate memory for extcon\n"); + ret = -ENOMEM; + goto err_irq; + } + info->edev->name = DEV_NAME; + info->edev->supported_cable = max8997_extcon_cable; + ret = extcon_dev_register(info->edev, NULL); + if (ret) { + dev_err(&pdev->dev, "failed to register extcon device\n"); + goto err_extcon; + } + /* Initialize registers according to platform data */ - max8997_initialize_device(info); + if (pdata->muic_pdata) { + struct max8997_muic_platform_data *mdata = info->muic_pdata; + + for (i = 0; i < mdata->num_init_data; i++) { + max8997_write_reg(info->muic, mdata->init_data[i].addr, + mdata->init_data[i].data); + } + } /* Initial device detection */ max8997_muic_detect_dev(info); return ret; +err_extcon: + kfree(info->edev); err_irq: while (--i >= 0) free_irq(pdata->irq_base + muic_irqs[i].irq, info); -err_pdata: kfree(info); err_kfree: return ret; @@ -464,14 +505,15 @@ err_kfree: static int __devexit max8997_muic_remove(struct platform_device *pdev) { struct max8997_muic_info *info = platform_get_drvdata(pdev); - struct max8997_platform_data *pdata = - dev_get_platdata(info->iodev->dev); + struct max8997_dev *max8997 = i2c_get_clientdata(info->muic); int i; for (i = 0; i < ARRAY_SIZE(muic_irqs); i++) - free_irq(pdata->irq_base + muic_irqs[i].irq, info); + free_irq(max8997->irq_base + muic_irqs[i].irq, info); cancel_work_sync(&info->irq_work); + extcon_dev_unregister(info->edev); + kfree(info); return 0; @@ -479,7 +521,7 @@ static int __devexit max8997_muic_remove(struct platform_device *pdev) static struct platform_driver max8997_muic_driver = { .driver = { - .name = "max8997-muic", + .name = DEV_NAME, .owner = THIS_MODULE, }, .probe = max8997_muic_probe, @@ -488,6 +530,6 @@ static struct platform_driver max8997_muic_driver = { module_platform_driver(max8997_muic_driver); -MODULE_DESCRIPTION("Maxim MAX8997 MUIC driver"); +MODULE_DESCRIPTION("Maxim MAX8997 Extcon driver"); MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); MODULE_LICENSE("GPL"); diff --git a/drivers/extcon/extcon_class.c b/drivers/extcon/extcon_class.c new file mode 100644 index 000000000000..f598a700ec15 --- /dev/null +++ b/drivers/extcon/extcon_class.c @@ -0,0 +1,832 @@ +/* + * drivers/extcon/extcon_class.c + * + * External connector (extcon) class driver + * + * Copyright (C) 2012 Samsung Electronics + * Author: Donggeun Kim <dg77.kim@samsung.com> + * Author: MyungJoo Ham <myungjoo.ham@samsung.com> + * + * based on android/drivers/switch/switch_class.c + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood <lockwood@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +*/ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/fs.h> +#include <linux/err.h> +#include <linux/extcon.h> +#include <linux/slab.h> + +/* + * extcon_cable_name suggests the standard cable names for commonly used + * cable types. + * + * However, please do not use extcon_cable_name directly for extcon_dev + * struct's supported_cable pointer unless your device really supports + * every single port-type of the following cable names. Please choose cable + * names that are actually used in your extcon device. + */ +const char *extcon_cable_name[] = { + [EXTCON_USB] = "USB", + [EXTCON_USB_HOST] = "USB-Host", + [EXTCON_TA] = "TA", + [EXTCON_FAST_CHARGER] = "Fast-charger", + [EXTCON_SLOW_CHARGER] = "Slow-charger", + [EXTCON_CHARGE_DOWNSTREAM] = "Charge-downstream", + [EXTCON_HDMI] = "HDMI", + [EXTCON_MHL] = "MHL", + [EXTCON_DVI] = "DVI", + [EXTCON_VGA] = "VGA", + [EXTCON_DOCK] = "Dock", + [EXTCON_LINE_IN] = "Line-in", + [EXTCON_LINE_OUT] = "Line-out", + [EXTCON_MIC_IN] = "Microphone", + [EXTCON_HEADPHONE_OUT] = "Headphone", + [EXTCON_SPDIF_IN] = "SPDIF-in", + [EXTCON_SPDIF_OUT] = "SPDIF-out", + [EXTCON_VIDEO_IN] = "Video-in", + [EXTCON_VIDEO_OUT] = "Video-out", + [EXTCON_MECHANICAL] = "Mechanical", + + NULL, +}; + +struct class *extcon_class; +#if defined(CONFIG_ANDROID) +static struct class_compat *switch_class; +#endif /* CONFIG_ANDROID */ + +static LIST_HEAD(extcon_dev_list); +static DEFINE_MUTEX(extcon_dev_list_lock); + +/** + * check_mutually_exclusive - Check if new_state violates mutually_exclusive + * condition. + * @edev: the extcon device + * @new_state: new cable attach status for @edev + * + * Returns 0 if nothing violates. Returns the index + 1 for the first + * violated condition. + */ +static int check_mutually_exclusive(struct extcon_dev *edev, u32 new_state) +{ + int i = 0; + + if (!edev->mutually_exclusive) + return 0; + + for (i = 0; edev->mutually_exclusive[i]; i++) { + int count = 0, j; + u32 correspondants = new_state & edev->mutually_exclusive[i]; + u32 exp = 1; + + for (j = 0; j < 32; j++) { + if (exp & correspondants) + count++; + if (count > 1) + return i + 1; + exp <<= 1; + } + } + + return 0; +} + +static ssize_t state_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int i, count = 0; + struct extcon_dev *edev = (struct extcon_dev *) dev_get_drvdata(dev); + + if (edev->print_state) { + int ret = edev->print_state(edev, buf); + + if (ret >= 0) + return ret; + /* Use default if failed */ + } + + if (edev->max_supported == 0) + return sprintf(buf, "%u\n", edev->state); + + for (i = 0; i < SUPPORTED_CABLE_MAX; i++) { + if (!edev->supported_cable[i]) + break; + count += sprintf(buf + count, "%s=%d\n", + edev->supported_cable[i], + !!(edev->state & (1 << i))); + } + + return count; +} + +int extcon_set_state(struct extcon_dev *edev, u32 state); +static ssize_t state_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + u32 state; + ssize_t ret = 0; + struct extcon_dev *edev = (struct extcon_dev *) dev_get_drvdata(dev); + + ret = sscanf(buf, "0x%x", &state); + if (ret == 0) + ret = -EINVAL; + else + ret = extcon_set_state(edev, state); + + if (ret < 0) + return ret; + + return count; +} + +static ssize_t name_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct extcon_dev *edev = (struct extcon_dev *) dev_get_drvdata(dev); + + /* Optional callback given by the user */ + if (edev->print_name) { + int ret = edev->print_name(edev, buf); + if (ret >= 0) + return ret; + } + + return sprintf(buf, "%s\n", dev_name(edev->dev)); +} + +static ssize_t cable_name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct extcon_cable *cable = container_of(attr, struct extcon_cable, + attr_name); + + return sprintf(buf, "%s\n", + cable->edev->supported_cable[cable->cable_index]); +} + +static ssize_t cable_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct extcon_cable *cable = container_of(attr, struct extcon_cable, + attr_state); + + return sprintf(buf, "%d\n", + extcon_get_cable_state_(cable->edev, + cable->cable_index)); +} + +static ssize_t cable_state_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct extcon_cable *cable = container_of(attr, struct extcon_cable, + attr_state); + int ret, state; + + ret = sscanf(buf, "%d", &state); + if (ret == 0) + ret = -EINVAL; + else + ret = extcon_set_cable_state_(cable->edev, cable->cable_index, + state); + + if (ret < 0) + return ret; + return count; +} + +/** + * extcon_update_state() - Update the cable attach states of the extcon device + * only for the masked bits. + * @edev: the extcon device + * @mask: the bit mask to designate updated bits. + * @state: new cable attach status for @edev + * + * Changing the state sends uevent with environment variable containing + * the name of extcon device (envp[0]) and the state output (envp[1]). + * Tizen uses this format for extcon device to get events from ports. + * Android uses this format as well. + * + * Note that the notifier provides which bits are changed in the state + * variable with the val parameter (second) to the callback. + */ +int extcon_update_state(struct extcon_dev *edev, u32 mask, u32 state) +{ + char name_buf[120]; + char state_buf[120]; + char *prop_buf; + char *envp[3]; + int env_offset = 0; + int length; + unsigned long flags; + + spin_lock_irqsave(&edev->lock, flags); + + if (edev->state != ((edev->state & ~mask) | (state & mask))) { + u32 old_state = edev->state; + + if (check_mutually_exclusive(edev, (edev->state & ~mask) | + (state & mask))) { + spin_unlock_irqrestore(&edev->lock, flags); + return -EPERM; + } + + edev->state &= ~mask; + edev->state |= state & mask; + + raw_notifier_call_chain(&edev->nh, old_state, edev); + + /* This could be in interrupt handler */ + prop_buf = (char *)get_zeroed_page(GFP_ATOMIC); + if (prop_buf) { + length = name_show(edev->dev, NULL, prop_buf); + if (length > 0) { + if (prop_buf[length - 1] == '\n') + prop_buf[length - 1] = 0; + snprintf(name_buf, sizeof(name_buf), + "NAME=%s", prop_buf); + envp[env_offset++] = name_buf; + } + length = state_show(edev->dev, NULL, prop_buf); + if (length > 0) { + if (prop_buf[length - 1] == '\n') + prop_buf[length - 1] = 0; + snprintf(state_buf, sizeof(state_buf), + "STATE=%s", prop_buf); + envp[env_offset++] = state_buf; + } + envp[env_offset] = NULL; + /* Unlock early before uevent */ + spin_unlock_irqrestore(&edev->lock, flags); + + kobject_uevent_env(&edev->dev->kobj, KOBJ_CHANGE, envp); + free_page((unsigned long)prop_buf); + } else { + /* Unlock early before uevent */ + spin_unlock_irqrestore(&edev->lock, flags); + + dev_err(edev->dev, "out of memory in extcon_set_state\n"); + kobject_uevent(&edev->dev->kobj, KOBJ_CHANGE); + } + } else { + /* No changes */ + spin_unlock_irqrestore(&edev->lock, flags); + } + + return 0; +} +EXPORT_SYMBOL_GPL(extcon_update_state); + +/** + * extcon_set_state() - Set the cable attach states of the extcon device. + * @edev: the extcon device + * @state: new cable attach status for @edev + * + * Note that notifier provides which bits are changed in the state + * variable with the val parameter (second) to the callback. + */ +int extcon_set_state(struct extcon_dev *edev, u32 state) +{ + return extcon_update_state(edev, 0xffffffff, state); +} +EXPORT_SYMBOL_GPL(extcon_set_state); + +/** + * extcon_find_cable_index() - Get the cable index based on the cable name. + * @edev: the extcon device that has the cable. + * @cable_name: cable name to be searched. + * + * Note that accessing a cable state based on cable_index is faster than + * cable_name because using cable_name induces a loop with strncmp(). + * Thus, when get/set_cable_state is repeatedly used, using cable_index + * is recommended. + */ +int extcon_find_cable_index(struct extcon_dev *edev, const char *cable_name) +{ + int i; + + if (edev->supported_cable) { + for (i = 0; edev->supported_cable[i]; i++) { + if (!strncmp(edev->supported_cable[i], + cable_name, CABLE_NAME_MAX)) + return i; + } + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(extcon_find_cable_index); + +/** + * extcon_get_cable_state_() - Get the status of a specific cable. + * @edev: the extcon device that has the cable. + * @index: cable index that can be retrieved by extcon_find_cable_index(). + */ +int extcon_get_cable_state_(struct extcon_dev *edev, int index) +{ + if (index < 0 || (edev->max_supported && edev->max_supported <= index)) + return -EINVAL; + + return !!(edev->state & (1 << index)); +} +EXPORT_SYMBOL_GPL(extcon_get_cable_state_); + +/** + * extcon_get_cable_state() - Get the status of a specific cable. + * @edev: the extcon device that has the cable. + * @cable_name: cable name. + * + * Note that this is slower than extcon_get_cable_state_. + */ +int extcon_get_cable_state(struct extcon_dev *edev, const char *cable_name) +{ + return extcon_get_cable_state_(edev, extcon_find_cable_index + (edev, cable_name)); +} +EXPORT_SYMBOL_GPL(extcon_get_cable_state); + +/** + * extcon_get_cable_state_() - Set the status of a specific cable. + * @edev: the extcon device that has the cable. + * @index: cable index that can be retrieved by extcon_find_cable_index(). + * @cable_state: the new cable status. The default semantics is + * true: attached / false: detached. + */ +int extcon_set_cable_state_(struct extcon_dev *edev, + int index, bool cable_state) +{ + u32 state; + + if (index < 0 || (edev->max_supported && edev->max_supported <= index)) + return -EINVAL; + + state = cable_state ? (1 << index) : 0; + return extcon_update_state(edev, 1 << index, state); +} +EXPORT_SYMBOL_GPL(extcon_set_cable_state_); + +/** + * extcon_get_cable_state() - Set the status of a specific cable. + * @edev: the extcon device that has the cable. + * @cable_name: cable name. + * @cable_state: the new cable status. The default semantics is + * true: attached / false: detached. + * + * Note that this is slower than extcon_set_cable_state_. + */ +int extcon_set_cable_state(struct extcon_dev *edev, + const char *cable_name, bool cable_state) +{ + return extcon_set_cable_state_(edev, extcon_find_cable_index + (edev, cable_name), cable_state); +} +EXPORT_SYMBOL_GPL(extcon_set_cable_state); + +/** + * extcon_get_extcon_dev() - Get the extcon device instance from the name + * @extcon_name: The extcon name provided with extcon_dev_register() + */ +struct extcon_dev *extcon_get_extcon_dev(const char *extcon_name) +{ + struct extcon_dev *sd; + + mutex_lock(&extcon_dev_list_lock); + list_for_each_entry(sd, &extcon_dev_list, entry) { + if (!strcmp(sd->name, extcon_name)) + goto out; + } + sd = NULL; +out: + mutex_unlock(&extcon_dev_list_lock); + return sd; +} +EXPORT_SYMBOL_GPL(extcon_get_extcon_dev); + +static int _call_per_cable(struct notifier_block *nb, unsigned long val, + void *ptr) +{ + struct extcon_specific_cable_nb *obj = container_of(nb, + struct extcon_specific_cable_nb, internal_nb); + struct extcon_dev *edev = ptr; + + if ((val & (1 << obj->cable_index)) != + (edev->state & (1 << obj->cable_index))) { + bool cable_state = true; + + obj->previous_value = val; + + if (val & (1 << obj->cable_index)) + cable_state = false; + + return obj->user_nb->notifier_call(obj->user_nb, + cable_state, ptr); + } + + return NOTIFY_OK; +} + +/** + * extcon_register_interest() - Register a notifier for a state change of a + * specific cable, not a entier set of cables of a + * extcon device. + * @obj: an empty extcon_specific_cable_nb object to be returned. + * @extcon_name: the name of extcon device. + * @cable_name: the target cable name. + * @nb: the notifier block to get notified. + * + * Provide an empty extcon_specific_cable_nb. extcon_register_interest() sets + * the struct for you. + * + * extcon_register_interest is a helper function for those who want to get + * notification for a single specific cable's status change. If a user wants + * to get notification for any changes of all cables of a extcon device, + * he/she should use the general extcon_register_notifier(). + * + * Note that the second parameter given to the callback of nb (val) is + * "old_state", not the current state. The current state can be retrieved + * by looking at the third pameter (edev pointer)'s state value. + */ +int extcon_register_interest(struct extcon_specific_cable_nb *obj, + const char *extcon_name, const char *cable_name, + struct notifier_block *nb) +{ + if (!obj || !extcon_name || !cable_name || !nb) + return -EINVAL; + + obj->edev = extcon_get_extcon_dev(extcon_name); + if (!obj->edev) + return -ENODEV; + + obj->cable_index = extcon_find_cable_index(obj->edev, cable_name); + if (obj->cable_index < 0) + return -ENODEV; + + obj->user_nb = nb; + + obj->internal_nb.notifier_call = _call_per_cable; + + return raw_notifier_chain_register(&obj->edev->nh, &obj->internal_nb); +} + +/** + * extcon_unregister_interest() - Unregister the notifier registered by + * extcon_register_interest(). + * @obj: the extcon_specific_cable_nb object returned by + * extcon_register_interest(). + */ +int extcon_unregister_interest(struct extcon_specific_cable_nb *obj) +{ + if (!obj) + return -EINVAL; + + return raw_notifier_chain_unregister(&obj->edev->nh, &obj->internal_nb); +} + +/** + * extcon_register_notifier() - Register a notifee to get notified by + * any attach status changes from the extcon. + * @edev: the extcon device. + * @nb: a notifier block to be registered. + * + * Note that the second parameter given to the callback of nb (val) is + * "old_state", not the current state. The current state can be retrieved + * by looking at the third pameter (edev pointer)'s state value. + */ +int extcon_register_notifier(struct extcon_dev *edev, + struct notifier_block *nb) +{ + return raw_notifier_chain_register(&edev->nh, nb); +} +EXPORT_SYMBOL_GPL(extcon_register_notifier); + +/** + * extcon_unregister_notifier() - Unregister a notifee from the extcon device. + * @edev: the extcon device. + * @nb: a registered notifier block to be unregistered. + */ +int extcon_unregister_notifier(struct extcon_dev *edev, + struct notifier_block *nb) +{ + return raw_notifier_chain_unregister(&edev->nh, nb); +} +EXPORT_SYMBOL_GPL(extcon_unregister_notifier); + +static struct device_attribute extcon_attrs[] = { + __ATTR(state, S_IRUGO | S_IWUSR, state_show, state_store), + __ATTR_RO(name), + __ATTR_NULL, +}; + +static int create_extcon_class(void) +{ + if (!extcon_class) { + extcon_class = class_create(THIS_MODULE, "extcon"); + if (IS_ERR(extcon_class)) + return PTR_ERR(extcon_class); + extcon_class->dev_attrs = extcon_attrs; + +#if defined(CONFIG_ANDROID) + switch_class = class_compat_register("switch"); + if (WARN(!switch_class, "cannot allocate")) + return -ENOMEM; +#endif /* CONFIG_ANDROID */ + } + + return 0; +} + +static void extcon_cleanup(struct extcon_dev *edev, bool skip) +{ + mutex_lock(&extcon_dev_list_lock); + list_del(&edev->entry); + mutex_unlock(&extcon_dev_list_lock); + + if (!skip && get_device(edev->dev)) { + int index; + + if (edev->mutually_exclusive && edev->max_supported) { + for (index = 0; edev->mutually_exclusive[index]; + index++) + kfree(edev->d_attrs_muex[index].attr.name); + kfree(edev->d_attrs_muex); + kfree(edev->attrs_muex); + } + + for (index = 0; index < edev->max_supported; index++) + kfree(edev->cables[index].attr_g.name); + + if (edev->max_supported) { + kfree(edev->extcon_dev_type.groups); + kfree(edev->cables); + } + + device_unregister(edev->dev); + put_device(edev->dev); + } + + kfree(edev->dev); +} + +static void extcon_dev_release(struct device *dev) +{ + struct extcon_dev *edev = (struct extcon_dev *) dev_get_drvdata(dev); + + extcon_cleanup(edev, true); +} + +static const char *muex_name = "mutually_exclusive"; +static void dummy_sysfs_dev_release(struct device *dev) +{ +} + +/** + * extcon_dev_register() - Register a new extcon device + * @edev : the new extcon device (should be allocated before calling) + * @dev : the parent device for this extcon device. + * + * Among the members of edev struct, please set the "user initializing data" + * in any case and set the "optional callbacks" if required. However, please + * do not set the values of "internal data", which are initialized by + * this function. + */ +int extcon_dev_register(struct extcon_dev *edev, struct device *dev) +{ + int ret, index = 0; + + if (!extcon_class) { + ret = create_extcon_class(); + if (ret < 0) + return ret; + } + + if (edev->supported_cable) { + /* Get size of array */ + for (index = 0; edev->supported_cable[index]; index++) + ; + edev->max_supported = index; + } else { + edev->max_supported = 0; + } + + if (index > SUPPORTED_CABLE_MAX) { + dev_err(edev->dev, "extcon: maximum number of supported cables exceeded.\n"); + return -EINVAL; + } + + edev->dev = kzalloc(sizeof(struct device), GFP_KERNEL); + if (!edev->dev) + return -ENOMEM; + edev->dev->parent = dev; + edev->dev->class = extcon_class; + edev->dev->release = extcon_dev_release; + + dev_set_name(edev->dev, edev->name ? edev->name : dev_name(dev)); + + if (edev->max_supported) { + char buf[10]; + char *str; + struct extcon_cable *cable; + + edev->cables = kzalloc(sizeof(struct extcon_cable) * + edev->max_supported, GFP_KERNEL); + if (!edev->cables) { + ret = -ENOMEM; + goto err_sysfs_alloc; + } + for (index = 0; index < edev->max_supported; index++) { + cable = &edev->cables[index]; + + snprintf(buf, 10, "cable.%d", index); + str = kzalloc(sizeof(char) * (strlen(buf) + 1), + GFP_KERNEL); + if (!str) { + for (index--; index >= 0; index--) { + cable = &edev->cables[index]; + kfree(cable->attr_g.name); + } + ret = -ENOMEM; + + goto err_alloc_cables; + } + strcpy(str, buf); + + cable->edev = edev; + cable->cable_index = index; + cable->attrs[0] = &cable->attr_name.attr; + cable->attrs[1] = &cable->attr_state.attr; + cable->attrs[2] = NULL; + cable->attr_g.name = str; + cable->attr_g.attrs = cable->attrs; + + cable->attr_name.attr.name = "name"; + cable->attr_name.attr.mode = 0444; + cable->attr_name.show = cable_name_show; + + cable->attr_state.attr.name = "state"; + cable->attr_state.attr.mode = 0644; + cable->attr_state.show = cable_state_show; + cable->attr_state.store = cable_state_store; + } + } + + if (edev->max_supported && edev->mutually_exclusive) { + char buf[80]; + char *name; + + /* Count the size of mutually_exclusive array */ + for (index = 0; edev->mutually_exclusive[index]; index++) + ; + + edev->attrs_muex = kzalloc(sizeof(struct attribute *) * + (index + 1), GFP_KERNEL); + if (!edev->attrs_muex) { + ret = -ENOMEM; + goto err_muex; + } + + edev->d_attrs_muex = kzalloc(sizeof(struct device_attribute) * + index, GFP_KERNEL); + if (!edev->d_attrs_muex) { + ret = -ENOMEM; + kfree(edev->attrs_muex); + goto err_muex; + } + + for (index = 0; edev->mutually_exclusive[index]; index++) { + sprintf(buf, "0x%x", edev->mutually_exclusive[index]); + name = kzalloc(sizeof(char) * (strlen(buf) + 1), + GFP_KERNEL); + if (!name) { + for (index--; index >= 0; index--) { + kfree(edev->d_attrs_muex[index].attr. + name); + } + kfree(edev->d_attrs_muex); + kfree(edev->attrs_muex); + ret = -ENOMEM; + goto err_muex; + } + strcpy(name, buf); + edev->d_attrs_muex[index].attr.name = name; + edev->d_attrs_muex[index].attr.mode = 0000; + edev->attrs_muex[index] = &edev->d_attrs_muex[index] + .attr; + } + edev->attr_g_muex.name = muex_name; + edev->attr_g_muex.attrs = edev->attrs_muex; + + } + + if (edev->max_supported) { + edev->extcon_dev_type.groups = + kzalloc(sizeof(struct attribute_group *) * + (edev->max_supported + 2), GFP_KERNEL); + if (!edev->extcon_dev_type.groups) { + ret = -ENOMEM; + goto err_alloc_groups; + } + + edev->extcon_dev_type.name = dev_name(edev->dev); + edev->extcon_dev_type.release = dummy_sysfs_dev_release; + + for (index = 0; index < edev->max_supported; index++) + edev->extcon_dev_type.groups[index] = + &edev->cables[index].attr_g; + if (edev->mutually_exclusive) + edev->extcon_dev_type.groups[index] = + &edev->attr_g_muex; + + edev->dev->type = &edev->extcon_dev_type; + } + + ret = device_register(edev->dev); + if (ret) { + put_device(edev->dev); + goto err_dev; + } +#if defined(CONFIG_ANDROID) + if (switch_class) + ret = class_compat_create_link(switch_class, edev->dev, + dev); +#endif /* CONFIG_ANDROID */ + + spin_lock_init(&edev->lock); + + RAW_INIT_NOTIFIER_HEAD(&edev->nh); + + dev_set_drvdata(edev->dev, edev); + edev->state = 0; + + mutex_lock(&extcon_dev_list_lock); + list_add(&edev->entry, &extcon_dev_list); + mutex_unlock(&extcon_dev_list_lock); + + return 0; + +err_dev: + if (edev->max_supported) + kfree(edev->extcon_dev_type.groups); +err_alloc_groups: + if (edev->max_supported && edev->mutually_exclusive) { + for (index = 0; edev->mutually_exclusive[index]; index++) + kfree(edev->d_attrs_muex[index].attr.name); + kfree(edev->d_attrs_muex); + kfree(edev->attrs_muex); + } +err_muex: + for (index = 0; index < edev->max_supported; index++) + kfree(edev->cables[index].attr_g.name); +err_alloc_cables: + if (edev->max_supported) + kfree(edev->cables); +err_sysfs_alloc: + kfree(edev->dev); + return ret; +} +EXPORT_SYMBOL_GPL(extcon_dev_register); + +/** + * extcon_dev_unregister() - Unregister the extcon device. + * @edev: the extcon device instance to be unregitered. + * + * Note that this does not call kfree(edev) because edev was not allocated + * by this class. + */ +void extcon_dev_unregister(struct extcon_dev *edev) +{ + extcon_cleanup(edev, false); +} +EXPORT_SYMBOL_GPL(extcon_dev_unregister); + +static int __init extcon_class_init(void) +{ + return create_extcon_class(); +} +module_init(extcon_class_init); + +static void __exit extcon_class_exit(void) +{ + class_destroy(extcon_class); +} +module_exit(extcon_class_exit); + +MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>"); +MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); +MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>"); +MODULE_DESCRIPTION("External connector (extcon) class driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/extcon/extcon_gpio.c b/drivers/extcon/extcon_gpio.c new file mode 100644 index 000000000000..fe7a07b47336 --- /dev/null +++ b/drivers/extcon/extcon_gpio.c @@ -0,0 +1,169 @@ +/* + * drivers/extcon/extcon_gpio.c + * + * Single-state GPIO extcon driver based on extcon class + * + * Copyright (C) 2008 Google, Inc. + * Author: Mike Lockwood <lockwood@android.com> + * + * Modified by MyungJoo Ham <myungjoo.ham@samsung.com> to support extcon + * (originally switch class is supported) + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +*/ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/extcon.h> +#include <linux/workqueue.h> +#include <linux/gpio.h> +#include <linux/extcon.h> +#include <linux/extcon/extcon_gpio.h> + +struct gpio_extcon_data { + struct extcon_dev edev; + unsigned gpio; + const char *state_on; + const char *state_off; + int irq; + struct delayed_work work; + unsigned long debounce_jiffies; +}; + +static void gpio_extcon_work(struct work_struct *work) +{ + int state; + struct gpio_extcon_data *data = + container_of(to_delayed_work(work), struct gpio_extcon_data, + work); + + state = gpio_get_value(data->gpio); + extcon_set_state(&data->edev, state); +} + +static irqreturn_t gpio_irq_handler(int irq, void *dev_id) +{ + struct gpio_extcon_data *extcon_data = dev_id; + + schedule_delayed_work(&extcon_data->work, + extcon_data->debounce_jiffies); + return IRQ_HANDLED; +} + +static ssize_t extcon_gpio_print_state(struct extcon_dev *edev, char *buf) +{ + struct gpio_extcon_data *extcon_data = + container_of(edev, struct gpio_extcon_data, edev); + const char *state; + if (extcon_get_state(edev)) + state = extcon_data->state_on; + else + state = extcon_data->state_off; + + if (state) + return sprintf(buf, "%s\n", state); + return -EINVAL; +} + +static int __devinit gpio_extcon_probe(struct platform_device *pdev) +{ + struct gpio_extcon_platform_data *pdata = pdev->dev.platform_data; + struct gpio_extcon_data *extcon_data; + int ret = 0; + + if (!pdata) + return -EBUSY; + if (!pdata->irq_flags) { + dev_err(&pdev->dev, "IRQ flag is not specified.\n"); + return -EINVAL; + } + + extcon_data = devm_kzalloc(&pdev->dev, sizeof(struct gpio_extcon_data), + GFP_KERNEL); + if (!extcon_data) + return -ENOMEM; + + extcon_data->edev.name = pdata->name; + extcon_data->gpio = pdata->gpio; + extcon_data->state_on = pdata->state_on; + extcon_data->state_off = pdata->state_off; + if (pdata->state_on && pdata->state_off) + extcon_data->edev.print_state = extcon_gpio_print_state; + extcon_data->debounce_jiffies = msecs_to_jiffies(pdata->debounce); + + ret = extcon_dev_register(&extcon_data->edev, &pdev->dev); + if (ret < 0) + goto err_extcon_dev_register; + + ret = gpio_request_one(extcon_data->gpio, GPIOF_DIR_IN, pdev->name); + if (ret < 0) + goto err_request_gpio; + + INIT_DELAYED_WORK(&extcon_data->work, gpio_extcon_work); + + extcon_data->irq = gpio_to_irq(extcon_data->gpio); + if (extcon_data->irq < 0) { + ret = extcon_data->irq; + goto err_detect_irq_num_failed; + } + + ret = request_any_context_irq(extcon_data->irq, gpio_irq_handler, + pdata->irq_flags, pdev->name, + extcon_data); + if (ret < 0) + goto err_request_irq; + + /* Perform initial detection */ + gpio_extcon_work(&extcon_data->work.work); + + return 0; + +err_request_irq: +err_detect_irq_num_failed: + gpio_free(extcon_data->gpio); +err_request_gpio: + extcon_dev_unregister(&extcon_data->edev); +err_extcon_dev_register: + devm_kfree(&pdev->dev, extcon_data); + + return ret; +} + +static int __devexit gpio_extcon_remove(struct platform_device *pdev) +{ + struct gpio_extcon_data *extcon_data = platform_get_drvdata(pdev); + + cancel_delayed_work_sync(&extcon_data->work); + gpio_free(extcon_data->gpio); + extcon_dev_unregister(&extcon_data->edev); + devm_kfree(&pdev->dev, extcon_data); + + return 0; +} + +static struct platform_driver gpio_extcon_driver = { + .probe = gpio_extcon_probe, + .remove = __devexit_p(gpio_extcon_remove), + .driver = { + .name = "extcon-gpio", + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(gpio_extcon_driver); + +MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>"); +MODULE_DESCRIPTION("GPIO extcon driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpio/devres.c b/drivers/gpio/devres.c index 3dd29399cef5..8950f6261bbb 100644 --- a/drivers/gpio/devres.c +++ b/drivers/gpio/devres.c @@ -83,8 +83,7 @@ EXPORT_SYMBOL(devm_gpio_request); void devm_gpio_free(struct device *dev, unsigned int gpio) { - WARN_ON(devres_destroy(dev, devm_gpio_release, devm_gpio_match, + WARN_ON(devres_release(dev, devm_gpio_release, devm_gpio_match, &gpio)); - gpio_free(gpio); } EXPORT_SYMBOL(devm_gpio_free); diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c index 9ffbfc575a0c..2b8b8d4558d2 100644 --- a/drivers/hv/channel_mgmt.c +++ b/drivers/hv/channel_mgmt.c @@ -46,40 +46,61 @@ struct vmbus_channel_message_table_entry { * * @icmsghdrp is of type &struct icmsg_hdr. * @negop is of type &struct icmsg_negotiate. - * Set up and fill in default negotiate response message. This response can - * come from both the vmbus driver and the hv_utils driver. The current api - * will respond properly to both Windows 2008 and Windows 2008-R2 operating - * systems. + * Set up and fill in default negotiate response message. + * + * The max_fw_version specifies the maximum framework version that + * we can support and max _srv_version specifies the maximum service + * version we can support. A special value MAX_SRV_VER can be + * specified to indicate that we can handle the maximum version + * exposed by the host. * * Mainly used by Hyper-V drivers. */ void vmbus_prep_negotiate_resp(struct icmsg_hdr *icmsghdrp, - struct icmsg_negotiate *negop, u8 *buf) + struct icmsg_negotiate *negop, u8 *buf, + int max_fw_version, int max_srv_version) { - if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) { - icmsghdrp->icmsgsize = 0x10; - - negop = (struct icmsg_negotiate *)&buf[ - sizeof(struct vmbuspipe_hdr) + - sizeof(struct icmsg_hdr)]; - - if (negop->icframe_vercnt == 2 && - negop->icversion_data[1].major == 3) { - negop->icversion_data[0].major = 3; - negop->icversion_data[0].minor = 0; - negop->icversion_data[1].major = 3; - negop->icversion_data[1].minor = 0; - } else { - negop->icversion_data[0].major = 1; - negop->icversion_data[0].minor = 0; - negop->icversion_data[1].major = 1; - negop->icversion_data[1].minor = 0; - } + int icframe_vercnt; + int icmsg_vercnt; + int i; + + icmsghdrp->icmsgsize = 0x10; + + negop = (struct icmsg_negotiate *)&buf[ + sizeof(struct vmbuspipe_hdr) + + sizeof(struct icmsg_hdr)]; + + icframe_vercnt = negop->icframe_vercnt; + icmsg_vercnt = negop->icmsg_vercnt; + + /* + * Select the framework version number we will + * support. + */ + + for (i = 0; i < negop->icframe_vercnt; i++) { + if (negop->icversion_data[i].major <= max_fw_version) + icframe_vercnt = negop->icversion_data[i].major; + } - negop->icframe_vercnt = 1; - negop->icmsg_vercnt = 1; + for (i = negop->icframe_vercnt; + (i < negop->icframe_vercnt + negop->icmsg_vercnt); i++) { + if (negop->icversion_data[i].major <= max_srv_version) + icmsg_vercnt = negop->icversion_data[i].major; } + + /* + * Respond with the maximum framework and service + * version numbers we can support. + */ + negop->icframe_vercnt = 1; + negop->icmsg_vercnt = 1; + negop->icversion_data[0].major = icframe_vercnt; + negop->icversion_data[0].minor = 0; + negop->icversion_data[1].major = icmsg_vercnt; + negop->icversion_data[1].minor = 0; } + EXPORT_SYMBOL_GPL(vmbus_prep_negotiate_resp); /* diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c index 15956bd48b48..86f8885aeb45 100644 --- a/drivers/hv/hv.c +++ b/drivers/hv/hv.c @@ -252,7 +252,7 @@ void hv_cleanup(void) * * This involves a hypercall. */ -u16 hv_post_message(union hv_connection_id connection_id, +int hv_post_message(union hv_connection_id connection_id, enum hv_message_type message_type, void *payload, size_t payload_size) { diff --git a/drivers/hv/hv_kvp.c b/drivers/hv/hv_kvp.c index 6186025209ce..0012eed6d872 100644 --- a/drivers/hv/hv_kvp.c +++ b/drivers/hv/hv_kvp.c @@ -394,7 +394,8 @@ void hv_kvp_onchannelcallback(void *context) sizeof(struct vmbuspipe_hdr)]; if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) { - vmbus_prep_negotiate_resp(icmsghdrp, negop, recv_buffer); + vmbus_prep_negotiate_resp(icmsghdrp, negop, + recv_buffer, MAX_SRV_VER, MAX_SRV_VER); } else { kvp_msg = (struct hv_kvp_msg *)&recv_buffer[ sizeof(struct vmbuspipe_hdr) + diff --git a/drivers/hv/hv_util.c b/drivers/hv/hv_util.c index dbb8b8eec210..d3ac6a40118b 100644 --- a/drivers/hv/hv_util.c +++ b/drivers/hv/hv_util.c @@ -70,7 +70,8 @@ static void shutdown_onchannelcallback(void *context) sizeof(struct vmbuspipe_hdr)]; if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) { - vmbus_prep_negotiate_resp(icmsghdrp, negop, shut_txf_buf); + vmbus_prep_negotiate_resp(icmsghdrp, negop, + shut_txf_buf, MAX_SRV_VER, MAX_SRV_VER); } else { shutdown_msg = (struct shutdown_msg_data *)&shut_txf_buf[ @@ -195,7 +196,8 @@ static void timesync_onchannelcallback(void *context) sizeof(struct vmbuspipe_hdr)]; if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) { - vmbus_prep_negotiate_resp(icmsghdrp, NULL, time_txf_buf); + vmbus_prep_negotiate_resp(icmsghdrp, NULL, time_txf_buf, + MAX_SRV_VER, MAX_SRV_VER); } else { timedatap = (struct ictimesync_data *)&time_txf_buf[ sizeof(struct vmbuspipe_hdr) + @@ -234,7 +236,8 @@ static void heartbeat_onchannelcallback(void *context) sizeof(struct vmbuspipe_hdr)]; if (icmsghdrp->icmsgtype == ICMSGTYPE_NEGOTIATE) { - vmbus_prep_negotiate_resp(icmsghdrp, NULL, hbeat_txf_buf); + vmbus_prep_negotiate_resp(icmsghdrp, NULL, + hbeat_txf_buf, MAX_SRV_VER, MAX_SRV_VER); } else { heartbeat_msg = (struct heartbeat_msg_data *)&hbeat_txf_buf[ diff --git a/drivers/hv/hyperv_vmbus.h b/drivers/hv/hyperv_vmbus.h index 699f0d8e59ed..b9426a6592ee 100644 --- a/drivers/hv/hyperv_vmbus.h +++ b/drivers/hv/hyperv_vmbus.h @@ -495,7 +495,7 @@ extern int hv_init(void); extern void hv_cleanup(void); -extern u16 hv_post_message(union hv_connection_id connection_id, +extern int hv_post_message(union hv_connection_id connection_id, enum hv_message_type message_type, void *payload, size_t payload_size); diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig new file mode 100644 index 000000000000..067f31174a0e --- /dev/null +++ b/drivers/memory/Kconfig @@ -0,0 +1,43 @@ +# +# Memory devices +# + +menuconfig MEMORY + bool "Memory Controller drivers" + +if MEMORY + +config TI_EMIF + tristate "Texas Instruments EMIF driver" + depends on ARCH_OMAP2PLUS + select DDR + help + This driver is for the EMIF module available in Texas Instruments + SoCs. EMIF is an SDRAM controller that, based on its revision, + supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. + This driver takes care of only LPDDR2 memories presently. The + functions of the driver includes re-configuring AC timing + parameters and other settings during frequency, voltage and + temperature changes + +config TEGRA20_MC + bool "Tegra20 Memory Controller(MC) driver" + default y + depends on ARCH_TEGRA_2x_SOC + help + This driver is for the Memory Controller(MC) module available + in Tegra20 SoCs, mainly for a address translation fault + analysis, especially for IOMMU/GART(Graphics Address + Relocation Table) module. + +config TEGRA30_MC + bool "Tegra30 Memory Controller(MC) driver" + default y + depends on ARCH_TEGRA_3x_SOC + help + This driver is for the Memory Controller(MC) module available + in Tegra30 SoCs, mainly for a address translation fault + analysis, especially for IOMMU/SMMU(System Memory Management + Unit) module. + +endif diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile new file mode 100644 index 000000000000..42b3ce9d80fc --- /dev/null +++ b/drivers/memory/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for memory devices +# + +obj-$(CONFIG_TI_EMIF) += emif.o +obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o +obj-$(CONFIG_TEGRA30_MC) += tegra30-mc.o diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c new file mode 100644 index 000000000000..33a4396b24cb --- /dev/null +++ b/drivers/memory/emif.c @@ -0,0 +1,1670 @@ +/* + * EMIF driver + * + * Copyright (C) 2012 Texas Instruments, Inc. + * + * Aneesh V <aneesh@ti.com> + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/reboot.h> +#include <linux/platform_data/emif_plat.h> +#include <linux/io.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/slab.h> +#include <linux/debugfs.h> +#include <linux/seq_file.h> +#include <linux/module.h> +#include <linux/list.h> +#include <linux/spinlock.h> +#include <memory/jedec_ddr.h> +#include "emif.h" + +/** + * struct emif_data - Per device static data for driver's use + * @duplicate: Whether the DDR devices attached to this EMIF + * instance are exactly same as that on EMIF1. In + * this case we can save some memory and processing + * @temperature_level: Maximum temperature of LPDDR2 devices attached + * to this EMIF - read from MR4 register. If there + * are two devices attached to this EMIF, this + * value is the maximum of the two temperature + * levels. + * @node: node in the device list + * @base: base address of memory-mapped IO registers. + * @dev: device pointer. + * @addressing table with addressing information from the spec + * @regs_cache: An array of 'struct emif_regs' that stores + * calculated register values for different + * frequencies, to avoid re-calculating them on + * each DVFS transition. + * @curr_regs: The set of register values used in the last + * frequency change (i.e. corresponding to the + * frequency in effect at the moment) + * @plat_data: Pointer to saved platform data. + * @debugfs_root: dentry to the root folder for EMIF in debugfs + */ +struct emif_data { + u8 duplicate; + u8 temperature_level; + u8 lpmode; + struct list_head node; + unsigned long irq_state; + void __iomem *base; + struct device *dev; + const struct lpddr2_addressing *addressing; + struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES]; + struct emif_regs *curr_regs; + struct emif_platform_data *plat_data; + struct dentry *debugfs_root; +}; + +static struct emif_data *emif1; +static spinlock_t emif_lock; +static unsigned long irq_state; +static u32 t_ck; /* DDR clock period in ps */ +static LIST_HEAD(device_list); + +static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif, + struct emif_regs *regs) +{ + u32 type = emif->plat_data->device_info->type; + u32 ip_rev = emif->plat_data->ip_rev; + + seq_printf(s, "EMIF register cache dump for %dMHz\n", + regs->freq/1000000); + + seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); + seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw); + seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw); + seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw); + + if (ip_rev == EMIF_4D) { + seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n", + regs->read_idle_ctrl_shdw_normal); + seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n", + regs->read_idle_ctrl_shdw_volt_ramp); + } else if (ip_rev == EMIF_4D5) { + seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n", + regs->dll_calib_ctrl_shdw_normal); + seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n", + regs->dll_calib_ctrl_shdw_volt_ramp); + } + + if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { + seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n", + regs->ref_ctrl_shdw_derated); + seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n", + regs->sdram_tim1_shdw_derated); + seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n", + regs->sdram_tim3_shdw_derated); + } +} + +static int emif_regdump_show(struct seq_file *s, void *unused) +{ + struct emif_data *emif = s->private; + struct emif_regs **regs_cache; + int i; + + if (emif->duplicate) + regs_cache = emif1->regs_cache; + else + regs_cache = emif->regs_cache; + + for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { + do_emif_regdump_show(s, emif, regs_cache[i]); + seq_printf(s, "\n"); + } + + return 0; +} + +static int emif_regdump_open(struct inode *inode, struct file *file) +{ + return single_open(file, emif_regdump_show, inode->i_private); +} + +static const struct file_operations emif_regdump_fops = { + .open = emif_regdump_open, + .read = seq_read, + .release = single_release, +}; + +static int emif_mr4_show(struct seq_file *s, void *unused) +{ + struct emif_data *emif = s->private; + + seq_printf(s, "MR4=%d\n", emif->temperature_level); + return 0; +} + +static int emif_mr4_open(struct inode *inode, struct file *file) +{ + return single_open(file, emif_mr4_show, inode->i_private); +} + +static const struct file_operations emif_mr4_fops = { + .open = emif_mr4_open, + .read = seq_read, + .release = single_release, +}; + +static int __init_or_module emif_debugfs_init(struct emif_data *emif) +{ + struct dentry *dentry; + int ret; + + dentry = debugfs_create_dir(dev_name(emif->dev), NULL); + if (IS_ERR(dentry)) { + ret = PTR_ERR(dentry); + goto err0; + } + emif->debugfs_root = dentry; + + dentry = debugfs_create_file("regcache_dump", S_IRUGO, + emif->debugfs_root, emif, &emif_regdump_fops); + if (IS_ERR(dentry)) { + ret = PTR_ERR(dentry); + goto err1; + } + + dentry = debugfs_create_file("mr4", S_IRUGO, + emif->debugfs_root, emif, &emif_mr4_fops); + if (IS_ERR(dentry)) { + ret = PTR_ERR(dentry); + goto err1; + } + + return 0; +err1: + debugfs_remove_recursive(emif->debugfs_root); +err0: + return ret; +} + +static void __exit emif_debugfs_exit(struct emif_data *emif) +{ + debugfs_remove_recursive(emif->debugfs_root); + emif->debugfs_root = NULL; +} + +/* + * Calculate the period of DDR clock from frequency value + */ +static void set_ddr_clk_period(u32 freq) +{ + /* Divide 10^12 by frequency to get period in ps */ + t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq); +} + +/* + * Get bus width used by EMIF. Note that this may be different from the + * bus width of the DDR devices used. For instance two 16-bit DDR devices + * may be connected to a given CS of EMIF. In this case bus width as far + * as EMIF is concerned is 32, where as the DDR bus width is 16 bits. + */ +static u32 get_emif_bus_width(struct emif_data *emif) +{ + u32 width; + void __iomem *base = emif->base; + + width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK) + >> NARROW_MODE_SHIFT; + width = width == 0 ? 32 : 16; + + return width; +} + +/* + * Get the CL from SDRAM_CONFIG register + */ +static u32 get_cl(struct emif_data *emif) +{ + u32 cl; + void __iomem *base = emif->base; + + cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT; + + return cl; +} + +static void set_lpmode(struct emif_data *emif, u8 lpmode) +{ + u32 temp; + void __iomem *base = emif->base; + + temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL); + temp &= ~LP_MODE_MASK; + temp |= (lpmode << LP_MODE_SHIFT); + writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL); +} + +static void do_freq_update(void) +{ + struct emif_data *emif; + + /* + * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE + * + * i728 DESCRIPTION: + * The EMIF automatically puts the SDRAM into self-refresh mode + * after the EMIF has not performed accesses during + * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles + * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set + * to 0x2. If during a small window the following three events + * occur: + * - The SR_TIMING counter expires + * - And frequency change is requested + * - And OCP access is requested + * Then it causes instable clock on the DDR interface. + * + * WORKAROUND + * To avoid the occurrence of the three events, the workaround + * is to disable the self-refresh when requesting a frequency + * change. Before requesting a frequency change the software must + * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the + * frequency change has been done, the software can reprogram + * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 + */ + list_for_each_entry(emif, &device_list, node) { + if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) + set_lpmode(emif, EMIF_LP_MODE_DISABLE); + } + + /* + * TODO: Do FREQ_UPDATE here when an API + * is available for this as part of the new + * clock framework + */ + + list_for_each_entry(emif, &device_list, node) { + if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) + set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); + } +} + +/* Find addressing table entry based on the device's type and density */ +static const struct lpddr2_addressing *get_addressing_table( + const struct ddr_device_info *device_info) +{ + u32 index, type, density; + + type = device_info->type; + density = device_info->density; + + switch (type) { + case DDR_TYPE_LPDDR2_S4: + index = density - 1; + break; + case DDR_TYPE_LPDDR2_S2: + switch (density) { + case DDR_DENSITY_1Gb: + case DDR_DENSITY_2Gb: + index = density + 3; + break; + default: + index = density - 1; + } + break; + default: + return NULL; + } + + return &lpddr2_jedec_addressing_table[index]; +} + +/* + * Find the the right timing table from the array of timing + * tables of the device using DDR clock frequency + */ +static const struct lpddr2_timings *get_timings_table(struct emif_data *emif, + u32 freq) +{ + u32 i, min, max, freq_nearest; + const struct lpddr2_timings *timings = NULL; + const struct lpddr2_timings *timings_arr = emif->plat_data->timings; + struct device *dev = emif->dev; + + /* Start with a very high frequency - 1GHz */ + freq_nearest = 1000000000; + + /* + * Find the timings table such that: + * 1. the frequency range covers the required frequency(safe) AND + * 2. the max_freq is closest to the required frequency(optimal) + */ + for (i = 0; i < emif->plat_data->timings_arr_size; i++) { + max = timings_arr[i].max_freq; + min = timings_arr[i].min_freq; + if ((freq >= min) && (freq <= max) && (max < freq_nearest)) { + freq_nearest = max; + timings = &timings_arr[i]; + } + } + + if (!timings) + dev_err(dev, "%s: couldn't find timings for - %dHz\n", + __func__, freq); + + dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n", + __func__, freq, freq_nearest); + + return timings; +} + +static u32 get_sdram_ref_ctrl_shdw(u32 freq, + const struct lpddr2_addressing *addressing) +{ + u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi; + + /* Scale down frequency and t_refi to avoid overflow */ + freq_khz = freq / 1000; + t_refi = addressing->tREFI_ns / 100; + + /* + * refresh rate to be set is 'tREFI(in us) * freq in MHz + * division by 10000 to account for change in units + */ + val = t_refi * freq_khz / 10000; + ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT; + + return ref_ctrl_shdw; +} + +static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing) +{ + u32 tim1 = 0, val = 0; + + val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; + tim1 |= val << T_WTR_SHIFT; + + if (addressing->num_banks == B8) + val = DIV_ROUND_UP(timings->tFAW, t_ck*4); + else + val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck)); + tim1 |= (val - 1) << T_RRD_SHIFT; + + val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1; + tim1 |= val << T_RC_SHIFT; + + val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck)); + tim1 |= (val - 1) << T_RAS_SHIFT; + + val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; + tim1 |= val << T_WR_SHIFT; + + val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1; + tim1 |= val << T_RCD_SHIFT; + + val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1; + tim1 |= val << T_RP_SHIFT; + + return tim1; +} + +static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing) +{ + u32 tim1 = 0, val = 0; + + val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; + tim1 = val << T_WTR_SHIFT; + + /* + * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps + * to tFAW for de-rating + */ + if (addressing->num_banks == B8) { + val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1; + } else { + val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck); + val = max(min_tck->tRRD, val) - 1; + } + tim1 |= val << T_RRD_SHIFT; + + val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck); + tim1 |= (val - 1) << T_RC_SHIFT; + + val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck); + val = max(min_tck->tRASmin, val) - 1; + tim1 |= val << T_RAS_SHIFT; + + val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; + tim1 |= val << T_WR_SHIFT; + + val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck)); + tim1 |= (val - 1) << T_RCD_SHIFT; + + val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck)); + tim1 |= (val - 1) << T_RP_SHIFT; + + return tim1; +} + +static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing, + u32 type) +{ + u32 tim2 = 0, val = 0; + + val = min_tck->tCKE - 1; + tim2 |= val << T_CKE_SHIFT; + + val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1; + tim2 |= val << T_RTP_SHIFT; + + /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */ + val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1; + tim2 |= val << T_XSNR_SHIFT; + + /* XSRD same as XSNR for LPDDR2 */ + tim2 |= val << T_XSRD_SHIFT; + + val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1; + tim2 |= val << T_XP_SHIFT; + + return tim2; +} + +static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing, + u32 type, u32 ip_rev, u32 derated) +{ + u32 tim3 = 0, val = 0, t_dqsck; + + val = timings->tRAS_max_ns / addressing->tREFI_ns - 1; + val = val > 0xF ? 0xF : val; + tim3 |= val << T_RAS_MAX_SHIFT; + + val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1; + tim3 |= val << T_RFC_SHIFT; + + t_dqsck = (derated == EMIF_DERATED_TIMINGS) ? + timings->tDQSCK_max_derated : timings->tDQSCK_max; + if (ip_rev == EMIF_4D5) + val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1; + else + val = DIV_ROUND_UP(t_dqsck, t_ck) - 1; + + tim3 |= val << T_TDQSCKMAX_SHIFT; + + val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1; + tim3 |= val << ZQ_ZQCS_SHIFT; + + val = DIV_ROUND_UP(timings->tCKESR, t_ck); + val = max(min_tck->tCKESR, val) - 1; + tim3 |= val << T_CKESR_SHIFT; + + if (ip_rev == EMIF_4D5) { + tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT; + + val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1; + tim3 |= val << T_PDLL_UL_SHIFT; + } + + return tim3; +} + +static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing, + bool cs1_used, bool cal_resistors_per_cs) +{ + u32 zq = 0, val = 0; + + val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns; + zq |= val << ZQ_REFINTERVAL_SHIFT; + + val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1; + zq |= val << ZQ_ZQCL_MULT_SHIFT; + + val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1; + zq |= val << ZQ_ZQINIT_MULT_SHIFT; + + zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT; + + if (cal_resistors_per_cs) + zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT; + else + zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT; + + zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */ + + val = cs1_used ? 1 : 0; + zq |= val << ZQ_CS1EN_SHIFT; + + return zq; +} + +static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing, + const struct emif_custom_configs *custom_configs, bool cs1_used, + u32 sdram_io_width, u32 emif_bus_width) +{ + u32 alert = 0, interval, devcnt; + + if (custom_configs && (custom_configs->mask & + EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)) + interval = custom_configs->temp_alert_poll_interval_ms; + else + interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS; + + interval *= 1000000; /* Convert to ns */ + interval /= addressing->tREFI_ns; /* Convert to refresh cycles */ + alert |= (interval << TA_REFINTERVAL_SHIFT); + + /* + * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width + * also to this form and subtract to get TA_DEVCNT, which is + * in log2(x) form. + */ + emif_bus_width = __fls(emif_bus_width) - 1; + devcnt = emif_bus_width - sdram_io_width; + alert |= devcnt << TA_DEVCNT_SHIFT; + + /* DEVWDT is in 'log2(x) - 3' form */ + alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT; + + alert |= 1 << TA_SFEXITEN_SHIFT; + alert |= 1 << TA_CS0EN_SHIFT; + alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT; + + return alert; +} + +static u32 get_read_idle_ctrl_shdw(u8 volt_ramp) +{ + u32 idle = 0, val = 0; + + /* + * Maximum value in normal conditions and increased frequency + * when voltage is ramping + */ + if (volt_ramp) + val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1; + else + val = 0x1FF; + + /* + * READ_IDLE_CTRL register in EMIF4D has same offset and fields + * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts + */ + idle |= val << DLL_CALIB_INTERVAL_SHIFT; + idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT; + + return idle; +} + +static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp) +{ + u32 calib = 0, val = 0; + + if (volt_ramp == DDR_VOLTAGE_RAMPING) + val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1; + else + val = 0; /* Disabled when voltage is stable */ + + calib |= val << DLL_CALIB_INTERVAL_SHIFT; + calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT; + + return calib; +} + +static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings, + u32 freq, u8 RL) +{ + u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0; + + val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1; + phy |= val << READ_LATENCY_SHIFT_4D; + + if (freq <= 100000000) + val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY; + else if (freq <= 200000000) + val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY; + else + val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY; + + phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D; + + return phy; +} + +static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl) +{ + u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay; + + /* + * DLL operates at 266 MHz. If DDR frequency is near 266 MHz, + * half-delay is not needed else set half-delay + */ + if (freq >= 265000000 && freq < 267000000) + half_delay = 0; + else + half_delay = 1; + + phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5; + phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS, + t_ck) - 1) << READ_LATENCY_SHIFT_4D5); + + return phy; +} + +static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void) +{ + u32 fifo_we_slave_ratio; + + fifo_we_slave_ratio = DIV_ROUND_CLOSEST( + EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); + + return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 | + fifo_we_slave_ratio << 22; +} + +static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void) +{ + u32 fifo_we_slave_ratio; + + fifo_we_slave_ratio = DIV_ROUND_CLOSEST( + EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); + + return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 | + fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23; +} + +static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void) +{ + u32 fifo_we_slave_ratio; + + fifo_we_slave_ratio = DIV_ROUND_CLOSEST( + EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); + + return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 | + fifo_we_slave_ratio << 13; +} + +static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev) +{ + u32 pwr_mgmt_ctrl = 0, timeout; + u32 lpmode = EMIF_LP_MODE_SELF_REFRESH; + u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE; + u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER; + u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD; + + struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs; + + if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) { + lpmode = cust_cfgs->lpmode; + timeout_perf = cust_cfgs->lpmode_timeout_performance; + timeout_pwr = cust_cfgs->lpmode_timeout_power; + freq_threshold = cust_cfgs->lpmode_freq_threshold; + } + + /* Timeout based on DDR frequency */ + timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr; + + /* The value to be set in register is "log2(timeout) - 3" */ + if (timeout < 16) { + timeout = 0; + } else { + timeout = __fls(timeout) - 3; + if (timeout & (timeout - 1)) + timeout++; + } + + switch (lpmode) { + case EMIF_LP_MODE_CLOCK_STOP: + pwr_mgmt_ctrl = (timeout << CS_TIM_SHIFT) | + SR_TIM_MASK | PD_TIM_MASK; + break; + case EMIF_LP_MODE_SELF_REFRESH: + /* Workaround for errata i735 */ + if (timeout < 6) + timeout = 6; + + pwr_mgmt_ctrl = (timeout << SR_TIM_SHIFT) | + CS_TIM_MASK | PD_TIM_MASK; + break; + case EMIF_LP_MODE_PWR_DN: + pwr_mgmt_ctrl = (timeout << PD_TIM_SHIFT) | + CS_TIM_MASK | SR_TIM_MASK; + break; + case EMIF_LP_MODE_DISABLE: + default: + pwr_mgmt_ctrl = CS_TIM_MASK | + PD_TIM_MASK | SR_TIM_MASK; + } + + /* No CS_TIM in EMIF_4D5 */ + if (ip_rev == EMIF_4D5) + pwr_mgmt_ctrl &= ~CS_TIM_MASK; + + pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT; + + return pwr_mgmt_ctrl; +} + +/* + * Get the temperature level of the EMIF instance: + * Reads the MR4 register of attached SDRAM parts to find out the temperature + * level. If there are two parts attached(one on each CS), then the temperature + * level for the EMIF instance is the higher of the two temperatures. + */ +static void get_temperature_level(struct emif_data *emif) +{ + u32 temp, temperature_level; + void __iomem *base; + + base = emif->base; + + /* Read mode register 4 */ + writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG); + temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA); + temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >> + MR4_SDRAM_REF_RATE_SHIFT; + + if (emif->plat_data->device_info->cs1_used) { + writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG); + temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA); + temp = (temp & MR4_SDRAM_REF_RATE_MASK) + >> MR4_SDRAM_REF_RATE_SHIFT; + temperature_level = max(temp, temperature_level); + } + + /* treat everything less than nominal(3) in MR4 as nominal */ + if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL)) + temperature_level = SDRAM_TEMP_NOMINAL; + + /* if we get reserved value in MR4 persist with the existing value */ + if (likely(temperature_level != SDRAM_TEMP_RESERVED_4)) + emif->temperature_level = temperature_level; +} + +/* + * Program EMIF shadow registers that are not dependent on temperature + * or voltage + */ +static void setup_registers(struct emif_data *emif, struct emif_regs *regs) +{ + void __iomem *base = emif->base; + + writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); + writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); + + /* Settings specific for EMIF4D5 */ + if (emif->plat_data->ip_rev != EMIF_4D5) + return; + writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW); + writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW); + writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW); +} + +/* + * When voltage ramps dll calibration and forced read idle should + * happen more often + */ +static void setup_volt_sensitive_regs(struct emif_data *emif, + struct emif_regs *regs, u32 volt_state) +{ + u32 calib_ctrl; + void __iomem *base = emif->base; + + /* + * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as + * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_* + * is an alias of the respective read_idle_ctrl_shdw_* (members of + * a union). So, the below code takes care of both cases + */ + if (volt_state == DDR_VOLTAGE_RAMPING) + calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp; + else + calib_ctrl = regs->dll_calib_ctrl_shdw_normal; + + writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW); +} + +/* + * setup_temperature_sensitive_regs() - set the timings for temperature + * sensitive registers. This happens once at initialisation time based + * on the temperature at boot time and subsequently based on the temperature + * alert interrupt. Temperature alert can happen when the temperature + * increases or drops. So this function can have the effect of either + * derating the timings or going back to nominal values. + */ +static void setup_temperature_sensitive_regs(struct emif_data *emif, + struct emif_regs *regs) +{ + u32 tim1, tim3, ref_ctrl, type; + void __iomem *base = emif->base; + u32 temperature; + + type = emif->plat_data->device_info->type; + + tim1 = regs->sdram_tim1_shdw; + tim3 = regs->sdram_tim3_shdw; + ref_ctrl = regs->ref_ctrl_shdw; + + /* No de-rating for non-lpddr2 devices */ + if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4) + goto out; + + temperature = emif->temperature_level; + if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) { + ref_ctrl = regs->ref_ctrl_shdw_derated; + } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) { + tim1 = regs->sdram_tim1_shdw_derated; + tim3 = regs->sdram_tim3_shdw_derated; + ref_ctrl = regs->ref_ctrl_shdw_derated; + } + +out: + writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); + writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW); + writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW); +} + +static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif) +{ + u32 old_temp_level; + irqreturn_t ret = IRQ_HANDLED; + + spin_lock_irqsave(&emif_lock, irq_state); + old_temp_level = emif->temperature_level; + get_temperature_level(emif); + + if (unlikely(emif->temperature_level == old_temp_level)) { + goto out; + } else if (!emif->curr_regs) { + dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); + goto out; + } + + if (emif->temperature_level < old_temp_level || + emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { + /* + * Temperature coming down - defer handling to thread OR + * Temperature far too high - do kernel_power_off() from + * thread context + */ + ret = IRQ_WAKE_THREAD; + } else { + /* Temperature is going up - handle immediately */ + setup_temperature_sensitive_regs(emif, emif->curr_regs); + do_freq_update(); + } + +out: + spin_unlock_irqrestore(&emif_lock, irq_state); + return ret; +} + +static irqreturn_t emif_interrupt_handler(int irq, void *dev_id) +{ + u32 interrupts; + struct emif_data *emif = dev_id; + void __iomem *base = emif->base; + struct device *dev = emif->dev; + irqreturn_t ret = IRQ_HANDLED; + + /* Save the status and clear it */ + interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); + writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); + + /* + * Handle temperature alert + * Temperature alert should be same for all ports + * So, it's enough to process it only for one of the ports + */ + if (interrupts & TA_SYS_MASK) + ret = handle_temp_alert(base, emif); + + if (interrupts & ERR_SYS_MASK) + dev_err(dev, "Access error from SYS port - %x\n", interrupts); + + if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { + /* Save the status and clear it */ + interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS); + writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS); + + if (interrupts & ERR_LL_MASK) + dev_err(dev, "Access error from LL port - %x\n", + interrupts); + } + + return ret; +} + +static irqreturn_t emif_threaded_isr(int irq, void *dev_id) +{ + struct emif_data *emif = dev_id; + + if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { + dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); + kernel_power_off(); + return IRQ_HANDLED; + } + + spin_lock_irqsave(&emif_lock, irq_state); + + if (emif->curr_regs) { + setup_temperature_sensitive_regs(emif, emif->curr_regs); + do_freq_update(); + } else { + dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); + } + + spin_unlock_irqrestore(&emif_lock, irq_state); + + return IRQ_HANDLED; +} + +static void clear_all_interrupts(struct emif_data *emif) +{ + void __iomem *base = emif->base; + + writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS), + base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); + if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) + writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS), + base + EMIF_LL_OCP_INTERRUPT_STATUS); +} + +static void disable_and_clear_all_interrupts(struct emif_data *emif) +{ + void __iomem *base = emif->base; + + /* Disable all interrupts */ + writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET), + base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR); + if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) + writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET), + base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR); + + /* Clear all interrupts */ + clear_all_interrupts(emif); +} + +static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq) +{ + u32 interrupts, type; + void __iomem *base = emif->base; + + type = emif->plat_data->device_info->type; + + clear_all_interrupts(emif); + + /* Enable interrupts for SYS interface */ + interrupts = EN_ERR_SYS_MASK; + if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) + interrupts |= EN_TA_SYS_MASK; + writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET); + + /* Enable interrupts for LL interface */ + if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { + /* TA need not be enabled for LL */ + interrupts = EN_ERR_LL_MASK; + writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET); + } + + /* setup IRQ handlers */ + return devm_request_threaded_irq(emif->dev, irq, + emif_interrupt_handler, + emif_threaded_isr, + 0, dev_name(emif->dev), + emif); + +} + +static void __init_or_module emif_onetime_settings(struct emif_data *emif) +{ + u32 pwr_mgmt_ctrl, zq, temp_alert_cfg; + void __iomem *base = emif->base; + const struct lpddr2_addressing *addressing; + const struct ddr_device_info *device_info; + + device_info = emif->plat_data->device_info; + addressing = get_addressing_table(device_info); + + /* + * Init power management settings + * We don't know the frequency yet. Use a high frequency + * value for a conservative timeout setting + */ + pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif, + emif->plat_data->ip_rev); + emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT; + writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL); + + /* Init ZQ calibration settings */ + zq = get_zq_config_reg(addressing, device_info->cs1_used, + device_info->cal_resistors_per_cs); + writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG); + + /* Check temperature level temperature level*/ + get_temperature_level(emif); + if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) + dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); + + /* Init temperature polling */ + temp_alert_cfg = get_temp_alert_config(addressing, + emif->plat_data->custom_configs, device_info->cs1_used, + device_info->io_width, get_emif_bus_width(emif)); + writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG); + + /* + * Program external PHY control registers that are not frequency + * dependent + */ + if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY) + return; + writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW); + writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW); + writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW); + writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW); + writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW); + writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW); + writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW); + writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW); + writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW); + writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW); + writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW); + writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW); + writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW); + writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW); + writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW); + writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW); + writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW); + writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW); + writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW); + writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW); + writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW); +} + +static void get_default_timings(struct emif_data *emif) +{ + struct emif_platform_data *pd = emif->plat_data; + + pd->timings = lpddr2_jedec_timings; + pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings); + + dev_warn(emif->dev, "%s: using default timings\n", __func__); +} + +static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type, + u32 ip_rev, struct device *dev) +{ + int valid; + + valid = (type == DDR_TYPE_LPDDR2_S4 || + type == DDR_TYPE_LPDDR2_S2) + && (density >= DDR_DENSITY_64Mb + && density <= DDR_DENSITY_8Gb) + && (io_width >= DDR_IO_WIDTH_8 + && io_width <= DDR_IO_WIDTH_32); + + /* Combinations of EMIF and PHY revisions that we support today */ + switch (ip_rev) { + case EMIF_4D: + valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY); + break; + case EMIF_4D5: + valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY); + break; + default: + valid = 0; + } + + if (!valid) + dev_err(dev, "%s: invalid DDR details\n", __func__); + return valid; +} + +static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs, + struct device *dev) +{ + int valid = 1; + + if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) && + (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE)) + valid = cust_cfgs->lpmode_freq_threshold && + cust_cfgs->lpmode_timeout_performance && + cust_cfgs->lpmode_timeout_power; + + if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL) + valid = valid && cust_cfgs->temp_alert_poll_interval_ms; + + if (!valid) + dev_warn(dev, "%s: invalid custom configs\n", __func__); + + return valid; +} + +static struct emif_data *__init_or_module get_device_details( + struct platform_device *pdev) +{ + u32 size; + struct emif_data *emif = NULL; + struct ddr_device_info *dev_info; + struct emif_custom_configs *cust_cfgs; + struct emif_platform_data *pd; + struct device *dev; + void *temp; + + pd = pdev->dev.platform_data; + dev = &pdev->dev; + + if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type, + pd->device_info->density, pd->device_info->io_width, + pd->phy_type, pd->ip_rev, dev))) { + dev_err(dev, "%s: invalid device data\n", __func__); + goto error; + } + + emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL); + temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); + dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); + + if (!emif || !pd || !dev_info) { + dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__); + goto error; + } + + memcpy(temp, pd, sizeof(*pd)); + pd = temp; + memcpy(dev_info, pd->device_info, sizeof(*dev_info)); + + pd->device_info = dev_info; + emif->plat_data = pd; + emif->dev = dev; + emif->temperature_level = SDRAM_TEMP_NOMINAL; + + /* + * For EMIF instances other than EMIF1 see if the devices connected + * are exactly same as on EMIF1(which is typically the case). If so, + * mark it as a duplicate of EMIF1 and skip copying timings data. + * This will save some memory and some computation later. + */ + emif->duplicate = emif1 && (memcmp(dev_info, + emif1->plat_data->device_info, + sizeof(struct ddr_device_info)) == 0); + + if (emif->duplicate) { + pd->timings = NULL; + pd->min_tck = NULL; + goto out; + } else if (emif1) { + dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", + __func__); + } + + /* + * Copy custom configs - ignore allocation error, if any, as + * custom_configs is not very critical + */ + cust_cfgs = pd->custom_configs; + if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) { + temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL); + if (temp) + memcpy(temp, cust_cfgs, sizeof(*cust_cfgs)); + else + dev_warn(dev, "%s:%d: allocation error\n", __func__, + __LINE__); + pd->custom_configs = temp; + } + + /* + * Copy timings and min-tck values from platform data. If it is not + * available or if memory allocation fails, use JEDEC defaults + */ + size = sizeof(struct lpddr2_timings) * pd->timings_arr_size; + if (pd->timings) { + temp = devm_kzalloc(dev, size, GFP_KERNEL); + if (temp) { + memcpy(temp, pd->timings, sizeof(*pd->timings)); + pd->timings = temp; + } else { + dev_warn(dev, "%s:%d: allocation error\n", __func__, + __LINE__); + get_default_timings(emif); + } + } else { + get_default_timings(emif); + } + + if (pd->min_tck) { + temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL); + if (temp) { + memcpy(temp, pd->min_tck, sizeof(*pd->min_tck)); + pd->min_tck = temp; + } else { + dev_warn(dev, "%s:%d: allocation error\n", __func__, + __LINE__); + pd->min_tck = &lpddr2_jedec_min_tck; + } + } else { + pd->min_tck = &lpddr2_jedec_min_tck; + } + +out: + return emif; + +error: + return NULL; +} + +static int __init_or_module emif_probe(struct platform_device *pdev) +{ + struct emif_data *emif; + struct resource *res; + int irq; + + emif = get_device_details(pdev); + if (!emif) { + pr_err("%s: error getting device data\n", __func__); + goto error; + } + + list_add(&emif->node, &device_list); + emif->addressing = get_addressing_table(emif->plat_data->device_info); + + /* Save pointers to each other in emif and device structures */ + emif->dev = &pdev->dev; + platform_set_drvdata(pdev, emif); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(emif->dev, "%s: error getting memory resource\n", + __func__); + goto error; + } + + emif->base = devm_request_and_ioremap(emif->dev, res); + if (!emif->base) { + dev_err(emif->dev, "%s: devm_request_and_ioremap() failed\n", + __func__); + goto error; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(emif->dev, "%s: error getting IRQ resource - %d\n", + __func__, irq); + goto error; + } + + emif_onetime_settings(emif); + emif_debugfs_init(emif); + disable_and_clear_all_interrupts(emif); + setup_interrupts(emif, irq); + + /* One-time actions taken on probing the first device */ + if (!emif1) { + emif1 = emif; + spin_lock_init(&emif_lock); + + /* + * TODO: register notifiers for frequency and voltage + * change here once the respective frameworks are + * available + */ + } + + dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n", + __func__, emif->base, irq); + + return 0; +error: + return -ENODEV; +} + +static int __exit emif_remove(struct platform_device *pdev) +{ + struct emif_data *emif = platform_get_drvdata(pdev); + + emif_debugfs_exit(emif); + + return 0; +} + +static void emif_shutdown(struct platform_device *pdev) +{ + struct emif_data *emif = platform_get_drvdata(pdev); + + disable_and_clear_all_interrupts(emif); +} + +static int get_emif_reg_values(struct emif_data *emif, u32 freq, + struct emif_regs *regs) +{ + u32 cs1_used, ip_rev, phy_type; + u32 cl, type; + const struct lpddr2_timings *timings; + const struct lpddr2_min_tck *min_tck; + const struct ddr_device_info *device_info; + const struct lpddr2_addressing *addressing; + struct emif_data *emif_for_calc; + struct device *dev; + const struct emif_custom_configs *custom_configs; + + dev = emif->dev; + /* + * If the devices on this EMIF instance is duplicate of EMIF1, + * use EMIF1 details for the calculation + */ + emif_for_calc = emif->duplicate ? emif1 : emif; + timings = get_timings_table(emif_for_calc, freq); + addressing = emif_for_calc->addressing; + if (!timings || !addressing) { + dev_err(dev, "%s: not enough data available for %dHz", + __func__, freq); + return -1; + } + + device_info = emif_for_calc->plat_data->device_info; + type = device_info->type; + cs1_used = device_info->cs1_used; + ip_rev = emif_for_calc->plat_data->ip_rev; + phy_type = emif_for_calc->plat_data->phy_type; + + min_tck = emif_for_calc->plat_data->min_tck; + custom_configs = emif_for_calc->plat_data->custom_configs; + + set_ddr_clk_period(freq); + + regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing); + regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck, + addressing); + regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck, + addressing, type); + regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck, + addressing, type, ip_rev, EMIF_NORMAL_TIMINGS); + + cl = get_cl(emif); + + if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) { + regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d( + timings, freq, cl); + } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) { + regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl); + regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5(); + regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5(); + regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5(); + } else { + return -1; + } + + /* Only timeout values in pwr_mgmt_ctrl_shdw register */ + regs->pwr_mgmt_ctrl_shdw = + get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) & + (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK); + + if (ip_rev & EMIF_4D) { + regs->read_idle_ctrl_shdw_normal = + get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE); + + regs->read_idle_ctrl_shdw_volt_ramp = + get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING); + } else if (ip_rev & EMIF_4D5) { + regs->dll_calib_ctrl_shdw_normal = + get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE); + + regs->dll_calib_ctrl_shdw_volt_ramp = + get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING); + } + + if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { + regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4, + addressing); + + regs->sdram_tim1_shdw_derated = + get_sdram_tim_1_shdw_derated(timings, min_tck, + addressing); + + regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings, + min_tck, addressing, type, ip_rev, + EMIF_DERATED_TIMINGS); + } + + regs->freq = freq; + + return 0; +} + +/* + * get_regs() - gets the cached emif_regs structure for a given EMIF instance + * given frequency(freq): + * + * As an optimisation, every EMIF instance other than EMIF1 shares the + * register cache with EMIF1 if the devices connected on this instance + * are same as that on EMIF1(indicated by the duplicate flag) + * + * If we do not have an entry corresponding to the frequency given, we + * allocate a new entry and calculate the values + * + * Upon finding the right reg dump, save it in curr_regs. It can be + * directly used for thermal de-rating and voltage ramping changes. + */ +static struct emif_regs *get_regs(struct emif_data *emif, u32 freq) +{ + int i; + struct emif_regs **regs_cache; + struct emif_regs *regs = NULL; + struct device *dev; + + dev = emif->dev; + if (emif->curr_regs && emif->curr_regs->freq == freq) { + dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq); + return emif->curr_regs; + } + + if (emif->duplicate) + regs_cache = emif1->regs_cache; + else + regs_cache = emif->regs_cache; + + for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { + if (regs_cache[i]->freq == freq) { + regs = regs_cache[i]; + dev_dbg(dev, + "%s: reg dump found in reg cache for %u Hz\n", + __func__, freq); + break; + } + } + + /* + * If we don't have an entry for this frequency in the cache create one + * and calculate the values + */ + if (!regs) { + regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC); + if (!regs) + return NULL; + + if (get_emif_reg_values(emif, freq, regs)) { + devm_kfree(emif->dev, regs); + return NULL; + } + + /* + * Now look for an un-used entry in the cache and save the + * newly created struct. If there are no free entries + * over-write the last entry + */ + for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) + ; + + if (i >= EMIF_MAX_NUM_FREQUENCIES) { + dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n", + __func__); + i = EMIF_MAX_NUM_FREQUENCIES - 1; + devm_kfree(emif->dev, regs_cache[i]); + } + regs_cache[i] = regs; + } + + return regs; +} + +static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state) +{ + dev_dbg(emif->dev, "%s: voltage notification : %d", __func__, + volt_state); + + if (!emif->curr_regs) { + dev_err(emif->dev, + "%s: volt-notify before registers are ready: %d\n", + __func__, volt_state); + return; + } + + setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state); +} + +/* + * TODO: voltage notify handling should be hooked up to + * regulator framework as soon as the necessary support + * is available in mainline kernel. This function is un-used + * right now. + */ +static void __attribute__((unused)) volt_notify_handling(u32 volt_state) +{ + struct emif_data *emif; + + spin_lock_irqsave(&emif_lock, irq_state); + + list_for_each_entry(emif, &device_list, node) + do_volt_notify_handling(emif, volt_state); + do_freq_update(); + + spin_unlock_irqrestore(&emif_lock, irq_state); +} + +static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq) +{ + struct emif_regs *regs; + + regs = get_regs(emif, new_freq); + if (!regs) + return; + + emif->curr_regs = regs; + + /* + * Update the shadow registers: + * Temperature and voltage-ramp sensitive settings are also configured + * in terms of DDR cycles. So, we need to update them too when there + * is a freq change + */ + dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz", + __func__, new_freq); + setup_registers(emif, regs); + setup_temperature_sensitive_regs(emif, regs); + setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE); + + /* + * Part of workaround for errata i728. See do_freq_update() + * for more details + */ + if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) + set_lpmode(emif, EMIF_LP_MODE_DISABLE); +} + +/* + * TODO: frequency notify handling should be hooked up to + * clock framework as soon as the necessary support is + * available in mainline kernel. This function is un-used + * right now. + */ +static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq) +{ + struct emif_data *emif; + + /* + * NOTE: we are taking the spin-lock here and releases it + * only in post-notifier. This doesn't look good and + * Sparse complains about it, but this seems to be + * un-avoidable. We need to lock a sequence of events + * that is split between EMIF and clock framework. + * + * 1. EMIF driver updates EMIF timings in shadow registers in the + * frequency pre-notify callback from clock framework + * 2. clock framework sets up the registers for the new frequency + * 3. clock framework initiates a hw-sequence that updates + * the frequency EMIF timings synchronously. + * + * All these 3 steps should be performed as an atomic operation + * vis-a-vis similar sequence in the EMIF interrupt handler + * for temperature events. Otherwise, there could be race + * conditions that could result in incorrect EMIF timings for + * a given frequency + */ + spin_lock_irqsave(&emif_lock, irq_state); + + list_for_each_entry(emif, &device_list, node) + do_freq_pre_notify_handling(emif, new_freq); +} + +static void do_freq_post_notify_handling(struct emif_data *emif) +{ + /* + * Part of workaround for errata i728. See do_freq_update() + * for more details + */ + if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) + set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); +} + +/* + * TODO: frequency notify handling should be hooked up to + * clock framework as soon as the necessary support is + * available in mainline kernel. This function is un-used + * right now. + */ +static void __attribute__((unused)) freq_post_notify_handling(void) +{ + struct emif_data *emif; + + list_for_each_entry(emif, &device_list, node) + do_freq_post_notify_handling(emif); + + /* + * Lock is done in pre-notify handler. See freq_pre_notify_handling() + * for more details + */ + spin_unlock_irqrestore(&emif_lock, irq_state); +} + +static struct platform_driver emif_driver = { + .remove = __exit_p(emif_remove), + .shutdown = emif_shutdown, + .driver = { + .name = "emif", + }, +}; + +static int __init_or_module emif_register(void) +{ + return platform_driver_probe(&emif_driver, emif_probe); +} + +static void __exit emif_unregister(void) +{ + platform_driver_unregister(&emif_driver); +} + +module_init(emif_register); +module_exit(emif_unregister); +MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:emif"); +MODULE_AUTHOR("Texas Instruments Inc"); diff --git a/drivers/memory/emif.h b/drivers/memory/emif.h new file mode 100644 index 000000000000..bfe08bae961a --- /dev/null +++ b/drivers/memory/emif.h @@ -0,0 +1,589 @@ +/* + * Defines for the EMIF driver + * + * Copyright (C) 2012 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __EMIF_H +#define __EMIF_H + +/* + * Maximum number of different frequencies supported by EMIF driver + * Determines the number of entries in the pointer array for register + * cache + */ +#define EMIF_MAX_NUM_FREQUENCIES 6 + +/* State of the core voltage */ +#define DDR_VOLTAGE_STABLE 0 +#define DDR_VOLTAGE_RAMPING 1 + +/* Defines for timing De-rating */ +#define EMIF_NORMAL_TIMINGS 0 +#define EMIF_DERATED_TIMINGS 1 + +/* Length of the forced read idle period in terms of cycles */ +#define EMIF_READ_IDLE_LEN_VAL 5 + +/* + * forced read idle interval to be used when voltage + * is changed as part of DVFS/DPS - 1ms + */ +#define READ_IDLE_INTERVAL_DVFS (1*1000000) + +/* + * Forced read idle interval to be used when voltage is stable + * 50us - or maximum value will do + */ +#define READ_IDLE_INTERVAL_NORMAL (50*1000000) + +/* DLL calibration interval when voltage is NOT stable - 1us */ +#define DLL_CALIB_INTERVAL_DVFS (1*1000000) + +#define DLL_CALIB_ACK_WAIT_VAL 5 + +/* Interval between ZQCS commands - hw team recommended value */ +#define EMIF_ZQCS_INTERVAL_US (50*1000) +/* Enable ZQ Calibration on exiting Self-refresh */ +#define ZQ_SFEXITEN_ENABLE 1 +/* + * ZQ Calibration simultaneously on both chip-selects: + * Needs one calibration resistor per CS + */ +#define ZQ_DUALCALEN_DISABLE 0 +#define ZQ_DUALCALEN_ENABLE 1 + +#define T_ZQCS_DEFAULT_NS 90 +#define T_ZQCL_DEFAULT_NS 360 +#define T_ZQINIT_DEFAULT_NS 1000 + +/* DPD_EN */ +#define DPD_DISABLE 0 +#define DPD_ENABLE 1 + +/* + * Default values for the low-power entry to be used if not provided by user. + * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512 + * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz + */ +#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048 +#define EMIF_LP_MODE_TIMEOUT_POWER 512 +#define EMIF_LP_MODE_FREQ_THRESHOLD 400000000 + +/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */ +#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000 +#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41 +#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80 +#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF + +/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */ +#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200 +#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000 + +/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */ +#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360 + +#define EMIF_T_CSTA 3 +#define EMIF_T_PDLL_UL 128 + +/* External PHY control registers magic values */ +#define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080 +#define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040 +#define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010 +#define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004 +#define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040 +#define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010 +#define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004 +#define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000 +#define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000 +#define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000 +#define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080 +#define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800 +#define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040 +#define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001 +#define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150 +#define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0 +#define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540 +#define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000 +#define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000 +#define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000 +#define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077 + +#define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200 + +/* Registers offset */ +#define EMIF_MODULE_ID_AND_REVISION 0x0000 +#define EMIF_STATUS 0x0004 +#define EMIF_SDRAM_CONFIG 0x0008 +#define EMIF_SDRAM_CONFIG_2 0x000c +#define EMIF_SDRAM_REFRESH_CONTROL 0x0010 +#define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014 +#define EMIF_SDRAM_TIMING_1 0x0018 +#define EMIF_SDRAM_TIMING_1_SHDW 0x001c +#define EMIF_SDRAM_TIMING_2 0x0020 +#define EMIF_SDRAM_TIMING_2_SHDW 0x0024 +#define EMIF_SDRAM_TIMING_3 0x0028 +#define EMIF_SDRAM_TIMING_3_SHDW 0x002c +#define EMIF_LPDDR2_NVM_TIMING 0x0030 +#define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034 +#define EMIF_POWER_MANAGEMENT_CONTROL 0x0038 +#define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c +#define EMIF_LPDDR2_MODE_REG_DATA 0x0040 +#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050 +#define EMIF_OCP_CONFIG 0x0054 +#define EMIF_OCP_CONFIG_VALUE_1 0x0058 +#define EMIF_OCP_CONFIG_VALUE_2 0x005c +#define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060 +#define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064 +#define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068 +#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c +#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070 +#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074 +#define EMIF_PERFORMANCE_COUNTER_1 0x0080 +#define EMIF_PERFORMANCE_COUNTER_2 0x0084 +#define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088 +#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c +#define EMIF_PERFORMANCE_COUNTER_TIME 0x0090 +#define EMIF_MISC_REG 0x0094 +#define EMIF_DLL_CALIB_CTRL 0x0098 +#define EMIF_DLL_CALIB_CTRL_SHDW 0x009c +#define EMIF_END_OF_INTERRUPT 0x00a0 +#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4 +#define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8 +#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac +#define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0 +#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4 +#define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8 +#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc +#define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0 +#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8 +#define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc +#define EMIF_OCP_ERROR_LOG 0x00d0 +#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4 +#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8 +#define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc +#define EMIF_DDR_PHY_CTRL_1 0x00e4 +#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8 +#define EMIF_DDR_PHY_CTRL_2 0x00ec +#define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100 +#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104 +#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108 +#define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120 +#define EMIF_COS_CONFIG 0x0124 +#define EMIF_PHY_STATUS_1 0x0140 +#define EMIF_PHY_STATUS_2 0x0144 +#define EMIF_PHY_STATUS_3 0x0148 +#define EMIF_PHY_STATUS_4 0x014c +#define EMIF_PHY_STATUS_5 0x0150 +#define EMIF_PHY_STATUS_6 0x0154 +#define EMIF_PHY_STATUS_7 0x0158 +#define EMIF_PHY_STATUS_8 0x015c +#define EMIF_PHY_STATUS_9 0x0160 +#define EMIF_PHY_STATUS_10 0x0164 +#define EMIF_PHY_STATUS_11 0x0168 +#define EMIF_PHY_STATUS_12 0x016c +#define EMIF_PHY_STATUS_13 0x0170 +#define EMIF_PHY_STATUS_14 0x0174 +#define EMIF_PHY_STATUS_15 0x0178 +#define EMIF_PHY_STATUS_16 0x017c +#define EMIF_PHY_STATUS_17 0x0180 +#define EMIF_PHY_STATUS_18 0x0184 +#define EMIF_PHY_STATUS_19 0x0188 +#define EMIF_PHY_STATUS_20 0x018c +#define EMIF_PHY_STATUS_21 0x0190 +#define EMIF_EXT_PHY_CTRL_1 0x0200 +#define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204 +#define EMIF_EXT_PHY_CTRL_2 0x0208 +#define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c +#define EMIF_EXT_PHY_CTRL_3 0x0210 +#define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214 +#define EMIF_EXT_PHY_CTRL_4 0x0218 +#define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c +#define EMIF_EXT_PHY_CTRL_5 0x0220 +#define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224 +#define EMIF_EXT_PHY_CTRL_6 0x0228 +#define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c +#define EMIF_EXT_PHY_CTRL_7 0x0230 +#define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234 +#define EMIF_EXT_PHY_CTRL_8 0x0238 +#define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c +#define EMIF_EXT_PHY_CTRL_9 0x0240 +#define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244 +#define EMIF_EXT_PHY_CTRL_10 0x0248 +#define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c +#define EMIF_EXT_PHY_CTRL_11 0x0250 +#define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254 +#define EMIF_EXT_PHY_CTRL_12 0x0258 +#define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c +#define EMIF_EXT_PHY_CTRL_13 0x0260 +#define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264 +#define EMIF_EXT_PHY_CTRL_14 0x0268 +#define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c +#define EMIF_EXT_PHY_CTRL_15 0x0270 +#define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274 +#define EMIF_EXT_PHY_CTRL_16 0x0278 +#define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c +#define EMIF_EXT_PHY_CTRL_17 0x0280 +#define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284 +#define EMIF_EXT_PHY_CTRL_18 0x0288 +#define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c +#define EMIF_EXT_PHY_CTRL_19 0x0290 +#define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294 +#define EMIF_EXT_PHY_CTRL_20 0x0298 +#define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c +#define EMIF_EXT_PHY_CTRL_21 0x02a0 +#define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4 +#define EMIF_EXT_PHY_CTRL_22 0x02a8 +#define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac +#define EMIF_EXT_PHY_CTRL_23 0x02b0 +#define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4 +#define EMIF_EXT_PHY_CTRL_24 0x02b8 +#define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc +#define EMIF_EXT_PHY_CTRL_25 0x02c0 +#define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4 +#define EMIF_EXT_PHY_CTRL_26 0x02c8 +#define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc +#define EMIF_EXT_PHY_CTRL_27 0x02d0 +#define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4 +#define EMIF_EXT_PHY_CTRL_28 0x02d8 +#define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc +#define EMIF_EXT_PHY_CTRL_29 0x02e0 +#define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4 +#define EMIF_EXT_PHY_CTRL_30 0x02e8 +#define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec + +/* Registers shifts and masks */ + +/* EMIF_MODULE_ID_AND_REVISION */ +#define SCHEME_SHIFT 30 +#define SCHEME_MASK (0x3 << 30) +#define MODULE_ID_SHIFT 16 +#define MODULE_ID_MASK (0xfff << 16) +#define RTL_VERSION_SHIFT 11 +#define RTL_VERSION_MASK (0x1f << 11) +#define MAJOR_REVISION_SHIFT 8 +#define MAJOR_REVISION_MASK (0x7 << 8) +#define MINOR_REVISION_SHIFT 0 +#define MINOR_REVISION_MASK (0x3f << 0) + +/* STATUS */ +#define BE_SHIFT 31 +#define BE_MASK (1 << 31) +#define DUAL_CLK_MODE_SHIFT 30 +#define DUAL_CLK_MODE_MASK (1 << 30) +#define FAST_INIT_SHIFT 29 +#define FAST_INIT_MASK (1 << 29) +#define RDLVLGATETO_SHIFT 6 +#define RDLVLGATETO_MASK (1 << 6) +#define RDLVLTO_SHIFT 5 +#define RDLVLTO_MASK (1 << 5) +#define WRLVLTO_SHIFT 4 +#define WRLVLTO_MASK (1 << 4) +#define PHY_DLL_READY_SHIFT 2 +#define PHY_DLL_READY_MASK (1 << 2) + +/* SDRAM_CONFIG */ +#define SDRAM_TYPE_SHIFT 29 +#define SDRAM_TYPE_MASK (0x7 << 29) +#define IBANK_POS_SHIFT 27 +#define IBANK_POS_MASK (0x3 << 27) +#define DDR_TERM_SHIFT 24 +#define DDR_TERM_MASK (0x7 << 24) +#define DDR2_DDQS_SHIFT 23 +#define DDR2_DDQS_MASK (1 << 23) +#define DYN_ODT_SHIFT 21 +#define DYN_ODT_MASK (0x3 << 21) +#define DDR_DISABLE_DLL_SHIFT 20 +#define DDR_DISABLE_DLL_MASK (1 << 20) +#define SDRAM_DRIVE_SHIFT 18 +#define SDRAM_DRIVE_MASK (0x3 << 18) +#define CWL_SHIFT 16 +#define CWL_MASK (0x3 << 16) +#define NARROW_MODE_SHIFT 14 +#define NARROW_MODE_MASK (0x3 << 14) +#define CL_SHIFT 10 +#define CL_MASK (0xf << 10) +#define ROWSIZE_SHIFT 7 +#define ROWSIZE_MASK (0x7 << 7) +#define IBANK_SHIFT 4 +#define IBANK_MASK (0x7 << 4) +#define EBANK_SHIFT 3 +#define EBANK_MASK (1 << 3) +#define PAGESIZE_SHIFT 0 +#define PAGESIZE_MASK (0x7 << 0) + +/* SDRAM_CONFIG_2 */ +#define CS1NVMEN_SHIFT 30 +#define CS1NVMEN_MASK (1 << 30) +#define EBANK_POS_SHIFT 27 +#define EBANK_POS_MASK (1 << 27) +#define RDBNUM_SHIFT 4 +#define RDBNUM_MASK (0x3 << 4) +#define RDBSIZE_SHIFT 0 +#define RDBSIZE_MASK (0x7 << 0) + +/* SDRAM_REFRESH_CONTROL */ +#define INITREF_DIS_SHIFT 31 +#define INITREF_DIS_MASK (1 << 31) +#define SRT_SHIFT 29 +#define SRT_MASK (1 << 29) +#define ASR_SHIFT 28 +#define ASR_MASK (1 << 28) +#define PASR_SHIFT 24 +#define PASR_MASK (0x7 << 24) +#define REFRESH_RATE_SHIFT 0 +#define REFRESH_RATE_MASK (0xffff << 0) + +/* SDRAM_TIMING_1 */ +#define T_RTW_SHIFT 29 +#define T_RTW_MASK (0x7 << 29) +#define T_RP_SHIFT 25 +#define T_RP_MASK (0xf << 25) +#define T_RCD_SHIFT 21 +#define T_RCD_MASK (0xf << 21) +#define T_WR_SHIFT 17 +#define T_WR_MASK (0xf << 17) +#define T_RAS_SHIFT 12 +#define T_RAS_MASK (0x1f << 12) +#define T_RC_SHIFT 6 +#define T_RC_MASK (0x3f << 6) +#define T_RRD_SHIFT 3 +#define T_RRD_MASK (0x7 << 3) +#define T_WTR_SHIFT 0 +#define T_WTR_MASK (0x7 << 0) + +/* SDRAM_TIMING_2 */ +#define T_XP_SHIFT 28 +#define T_XP_MASK (0x7 << 28) +#define T_ODT_SHIFT 25 +#define T_ODT_MASK (0x7 << 25) +#define T_XSNR_SHIFT 16 +#define T_XSNR_MASK (0x1ff << 16) +#define T_XSRD_SHIFT 6 +#define T_XSRD_MASK (0x3ff << 6) +#define T_RTP_SHIFT 3 +#define T_RTP_MASK (0x7 << 3) +#define T_CKE_SHIFT 0 +#define T_CKE_MASK (0x7 << 0) + +/* SDRAM_TIMING_3 */ +#define T_PDLL_UL_SHIFT 28 +#define T_PDLL_UL_MASK (0xf << 28) +#define T_CSTA_SHIFT 24 +#define T_CSTA_MASK (0xf << 24) +#define T_CKESR_SHIFT 21 +#define T_CKESR_MASK (0x7 << 21) +#define ZQ_ZQCS_SHIFT 15 +#define ZQ_ZQCS_MASK (0x3f << 15) +#define T_TDQSCKMAX_SHIFT 13 +#define T_TDQSCKMAX_MASK (0x3 << 13) +#define T_RFC_SHIFT 4 +#define T_RFC_MASK (0x1ff << 4) +#define T_RAS_MAX_SHIFT 0 +#define T_RAS_MAX_MASK (0xf << 0) + +/* POWER_MANAGEMENT_CONTROL */ +#define PD_TIM_SHIFT 12 +#define PD_TIM_MASK (0xf << 12) +#define DPD_EN_SHIFT 11 +#define DPD_EN_MASK (1 << 11) +#define LP_MODE_SHIFT 8 +#define LP_MODE_MASK (0x7 << 8) +#define SR_TIM_SHIFT 4 +#define SR_TIM_MASK (0xf << 4) +#define CS_TIM_SHIFT 0 +#define CS_TIM_MASK (0xf << 0) + +/* LPDDR2_MODE_REG_DATA */ +#define VALUE_0_SHIFT 0 +#define VALUE_0_MASK (0x7f << 0) + +/* LPDDR2_MODE_REG_CONFIG */ +#define CS_SHIFT 31 +#define CS_MASK (1 << 31) +#define REFRESH_EN_SHIFT 30 +#define REFRESH_EN_MASK (1 << 30) +#define ADDRESS_SHIFT 0 +#define ADDRESS_MASK (0xff << 0) + +/* OCP_CONFIG */ +#define SYS_THRESH_MAX_SHIFT 24 +#define SYS_THRESH_MAX_MASK (0xf << 24) +#define MPU_THRESH_MAX_SHIFT 20 +#define MPU_THRESH_MAX_MASK (0xf << 20) +#define LL_THRESH_MAX_SHIFT 16 +#define LL_THRESH_MAX_MASK (0xf << 16) + +/* PERFORMANCE_COUNTER_1 */ +#define COUNTER1_SHIFT 0 +#define COUNTER1_MASK (0xffffffff << 0) + +/* PERFORMANCE_COUNTER_2 */ +#define COUNTER2_SHIFT 0 +#define COUNTER2_MASK (0xffffffff << 0) + +/* PERFORMANCE_COUNTER_CONFIG */ +#define CNTR2_MCONNID_EN_SHIFT 31 +#define CNTR2_MCONNID_EN_MASK (1 << 31) +#define CNTR2_REGION_EN_SHIFT 30 +#define CNTR2_REGION_EN_MASK (1 << 30) +#define CNTR2_CFG_SHIFT 16 +#define CNTR2_CFG_MASK (0xf << 16) +#define CNTR1_MCONNID_EN_SHIFT 15 +#define CNTR1_MCONNID_EN_MASK (1 << 15) +#define CNTR1_REGION_EN_SHIFT 14 +#define CNTR1_REGION_EN_MASK (1 << 14) +#define CNTR1_CFG_SHIFT 0 +#define CNTR1_CFG_MASK (0xf << 0) + +/* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */ +#define MCONNID2_SHIFT 24 +#define MCONNID2_MASK (0xff << 24) +#define REGION_SEL2_SHIFT 16 +#define REGION_SEL2_MASK (0x3 << 16) +#define MCONNID1_SHIFT 8 +#define MCONNID1_MASK (0xff << 8) +#define REGION_SEL1_SHIFT 0 +#define REGION_SEL1_MASK (0x3 << 0) + +/* PERFORMANCE_COUNTER_TIME */ +#define TOTAL_TIME_SHIFT 0 +#define TOTAL_TIME_MASK (0xffffffff << 0) + +/* DLL_CALIB_CTRL */ +#define ACK_WAIT_SHIFT 16 +#define ACK_WAIT_MASK (0xf << 16) +#define DLL_CALIB_INTERVAL_SHIFT 0 +#define DLL_CALIB_INTERVAL_MASK (0x1ff << 0) + +/* END_OF_INTERRUPT */ +#define EOI_SHIFT 0 +#define EOI_MASK (1 << 0) + +/* SYSTEM_OCP_INTERRUPT_RAW_STATUS */ +#define DNV_SYS_SHIFT 2 +#define DNV_SYS_MASK (1 << 2) +#define TA_SYS_SHIFT 1 +#define TA_SYS_MASK (1 << 1) +#define ERR_SYS_SHIFT 0 +#define ERR_SYS_MASK (1 << 0) + +/* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */ +#define DNV_LL_SHIFT 2 +#define DNV_LL_MASK (1 << 2) +#define TA_LL_SHIFT 1 +#define TA_LL_MASK (1 << 1) +#define ERR_LL_SHIFT 0 +#define ERR_LL_MASK (1 << 0) + +/* SYSTEM_OCP_INTERRUPT_ENABLE_SET */ +#define EN_DNV_SYS_SHIFT 2 +#define EN_DNV_SYS_MASK (1 << 2) +#define EN_TA_SYS_SHIFT 1 +#define EN_TA_SYS_MASK (1 << 1) +#define EN_ERR_SYS_SHIFT 0 +#define EN_ERR_SYS_MASK (1 << 0) + +/* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */ +#define EN_DNV_LL_SHIFT 2 +#define EN_DNV_LL_MASK (1 << 2) +#define EN_TA_LL_SHIFT 1 +#define EN_TA_LL_MASK (1 << 1) +#define EN_ERR_LL_SHIFT 0 +#define EN_ERR_LL_MASK (1 << 0) + +/* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */ +#define ZQ_CS1EN_SHIFT 31 +#define ZQ_CS1EN_MASK (1 << 31) +#define ZQ_CS0EN_SHIFT 30 +#define ZQ_CS0EN_MASK (1 << 30) +#define ZQ_DUALCALEN_SHIFT 29 +#define ZQ_DUALCALEN_MASK (1 << 29) +#define ZQ_SFEXITEN_SHIFT 28 +#define ZQ_SFEXITEN_MASK (1 << 28) +#define ZQ_ZQINIT_MULT_SHIFT 18 +#define ZQ_ZQINIT_MULT_MASK (0x3 << 18) +#define ZQ_ZQCL_MULT_SHIFT 16 +#define ZQ_ZQCL_MULT_MASK (0x3 << 16) +#define ZQ_REFINTERVAL_SHIFT 0 +#define ZQ_REFINTERVAL_MASK (0xffff << 0) + +/* TEMPERATURE_ALERT_CONFIG */ +#define TA_CS1EN_SHIFT 31 +#define TA_CS1EN_MASK (1 << 31) +#define TA_CS0EN_SHIFT 30 +#define TA_CS0EN_MASK (1 << 30) +#define TA_SFEXITEN_SHIFT 28 +#define TA_SFEXITEN_MASK (1 << 28) +#define TA_DEVWDT_SHIFT 26 +#define TA_DEVWDT_MASK (0x3 << 26) +#define TA_DEVCNT_SHIFT 24 +#define TA_DEVCNT_MASK (0x3 << 24) +#define TA_REFINTERVAL_SHIFT 0 +#define TA_REFINTERVAL_MASK (0x3fffff << 0) + +/* OCP_ERROR_LOG */ +#define MADDRSPACE_SHIFT 14 +#define MADDRSPACE_MASK (0x3 << 14) +#define MBURSTSEQ_SHIFT 11 +#define MBURSTSEQ_MASK (0x7 << 11) +#define MCMD_SHIFT 8 +#define MCMD_MASK (0x7 << 8) +#define MCONNID_SHIFT 0 +#define MCONNID_MASK (0xff << 0) + +/* DDR_PHY_CTRL_1 - EMIF4D */ +#define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4 +#define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4) +#define READ_LATENCY_SHIFT_4D 0 +#define READ_LATENCY_MASK_4D (0xf << 0) + +/* DDR_PHY_CTRL_1 - EMIF4D5 */ +#define DLL_HALF_DELAY_SHIFT_4D5 21 +#define DLL_HALF_DELAY_MASK_4D5 (1 << 21) +#define READ_LATENCY_SHIFT_4D5 0 +#define READ_LATENCY_MASK_4D5 (0x1f << 0) + +/* DDR_PHY_CTRL_1_SHDW */ +#define DDR_PHY_CTRL_1_SHDW_SHIFT 5 +#define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5) +#define READ_LATENCY_SHDW_SHIFT 0 +#define READ_LATENCY_SHDW_MASK (0x1f << 0) + +#ifndef __ASSEMBLY__ +/* + * Structure containing shadow of important registers in EMIF + * The calculation function fills in this structure to be later used for + * initialisation and DVFS + */ +struct emif_regs { + u32 freq; + u32 ref_ctrl_shdw; + u32 ref_ctrl_shdw_derated; + u32 sdram_tim1_shdw; + u32 sdram_tim1_shdw_derated; + u32 sdram_tim2_shdw; + u32 sdram_tim3_shdw; + u32 sdram_tim3_shdw_derated; + u32 pwr_mgmt_ctrl_shdw; + union { + u32 read_idle_ctrl_shdw_normal; + u32 dll_calib_ctrl_shdw_normal; + }; + union { + u32 read_idle_ctrl_shdw_volt_ramp; + u32 dll_calib_ctrl_shdw_volt_ramp; + }; + + u32 phy_ctrl_1_shdw; + u32 ext_phy_ctrl_2_shdw; + u32 ext_phy_ctrl_3_shdw; + u32 ext_phy_ctrl_4_shdw; +}; +#endif /* __ASSEMBLY__ */ +#endif /* __EMIF_H */ diff --git a/drivers/memory/tegra20-mc.c b/drivers/memory/tegra20-mc.c new file mode 100644 index 000000000000..3ed49c1c2b91 --- /dev/null +++ b/drivers/memory/tegra20-mc.c @@ -0,0 +1,257 @@ +/* + * Tegra20 Memory Controller + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/ratelimit.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/io.h> + +#define DRV_NAME "tegra20-mc" + +#define MC_INTSTATUS 0x0 +#define MC_INTMASK 0x4 + +#define MC_INT_ERR_SHIFT 6 +#define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT) +#define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT) +#define MC_INT_INVALID_GART_PAGE BIT(MC_INT_ERR_SHIFT + 1) +#define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2) +#define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3) + +#define MC_GART_ERROR_REQ 0x30 +#define MC_DECERR_EMEM_OTHERS_STATUS 0x58 +#define MC_SECURITY_VIOLATION_STATUS 0x74 + +#define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */ + +#define MC_CLIENT_ID_MASK 0x3f + +#define NUM_MC_REG_BANKS 2 + +struct tegra20_mc { + void __iomem *regs[NUM_MC_REG_BANKS]; + struct device *dev; +}; + +static inline u32 mc_readl(struct tegra20_mc *mc, u32 offs) +{ + u32 val = 0; + + if (offs < 0x24) + val = readl(mc->regs[0] + offs); + if (offs < 0x400) + val = readl(mc->regs[1] + offs - 0x3c); + + return val; +} + +static inline void mc_writel(struct tegra20_mc *mc, u32 val, u32 offs) +{ + if (offs < 0x24) { + writel(val, mc->regs[0] + offs); + return; + } + if (offs < 0x400) { + writel(val, mc->regs[1] + offs - 0x3c); + return; + } +} + +static const char * const tegra20_mc_client[] = { + "cbr_display0a", + "cbr_display0ab", + "cbr_display0b", + "cbr_display0bb", + "cbr_display0c", + "cbr_display0cb", + "cbr_display1b", + "cbr_display1bb", + "cbr_eppup", + "cbr_g2pr", + "cbr_g2sr", + "cbr_mpeunifbr", + "cbr_viruv", + "csr_avpcarm7r", + "csr_displayhc", + "csr_displayhcb", + "csr_fdcdrd", + "csr_g2dr", + "csr_host1xdmar", + "csr_host1xr", + "csr_idxsrd", + "csr_mpcorer", + "csr_mpe_ipred", + "csr_mpeamemrd", + "csr_mpecsrd", + "csr_ppcsahbdmar", + "csr_ppcsahbslvr", + "csr_texsrd", + "csr_vdebsevr", + "csr_vdember", + "csr_vdemcer", + "csr_vdetper", + "cbw_eppu", + "cbw_eppv", + "cbw_eppy", + "cbw_mpeunifbw", + "cbw_viwsb", + "cbw_viwu", + "cbw_viwv", + "cbw_viwy", + "ccw_g2dw", + "csw_avpcarm7w", + "csw_fdcdwr", + "csw_host1xw", + "csw_ispw", + "csw_mpcorew", + "csw_mpecswr", + "csw_ppcsahbdmaw", + "csw_ppcsahbslvw", + "csw_vdebsevw", + "csw_vdembew", + "csw_vdetpmw", +}; + +static void tegra20_mc_decode(struct tegra20_mc *mc, int n) +{ + u32 addr, req; + const char *client = "Unknown"; + int idx, cid; + const struct reg_info { + u32 offset; + u32 write_bit; /* 0=READ, 1=WRITE */ + int cid_shift; + char *message; + } reg[] = { + { + .offset = MC_DECERR_EMEM_OTHERS_STATUS, + .write_bit = 31, + .message = "MC_DECERR", + }, + { + .offset = MC_GART_ERROR_REQ, + .cid_shift = 1, + .message = "MC_GART_ERR", + + }, + { + .offset = MC_SECURITY_VIOLATION_STATUS, + .write_bit = 31, + .message = "MC_SECURITY_ERR", + }, + }; + + idx = n - MC_INT_ERR_SHIFT; + if ((idx < 0) || (idx >= ARRAY_SIZE(reg))) { + dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n", + BIT(n)); + return; + } + + req = mc_readl(mc, reg[idx].offset); + cid = (req >> reg[idx].cid_shift) & MC_CLIENT_ID_MASK; + if (cid < ARRAY_SIZE(tegra20_mc_client)) + client = tegra20_mc_client[cid]; + + addr = mc_readl(mc, reg[idx].offset + sizeof(u32)); + + dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s)\n", + reg[idx].message, req, addr, client, + (req & BIT(reg[idx].write_bit)) ? "write" : "read", + (reg[idx].offset == MC_SECURITY_VIOLATION_STATUS) ? + ((req & SECURITY_VIOLATION_TYPE) ? + "carveout" : "trustzone") : ""); +} + +static const struct of_device_id tegra20_mc_of_match[] __devinitconst = { + { .compatible = "nvidia,tegra20-mc", }, + {}, +}; + +static irqreturn_t tegra20_mc_isr(int irq, void *data) +{ + u32 stat, mask, bit; + struct tegra20_mc *mc = data; + + stat = mc_readl(mc, MC_INTSTATUS); + mask = mc_readl(mc, MC_INTMASK); + mask &= stat; + if (!mask) + return IRQ_NONE; + while ((bit = ffs(mask)) != 0) + tegra20_mc_decode(mc, bit - 1); + mc_writel(mc, stat, MC_INTSTATUS); + return IRQ_HANDLED; +} + +static int __devinit tegra20_mc_probe(struct platform_device *pdev) +{ + struct resource *irq; + struct tegra20_mc *mc; + int i, err; + u32 intmask; + + mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); + if (!mc) + return -ENOMEM; + mc->dev = &pdev->dev; + + for (i = 0; i < ARRAY_SIZE(mc->regs); i++) { + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) + return -ENODEV; + mc->regs[i] = devm_request_and_ioremap(&pdev->dev, res); + if (!mc->regs[i]) + return -EBUSY; + } + + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!irq) + return -ENODEV; + err = devm_request_irq(&pdev->dev, irq->start, tegra20_mc_isr, + IRQF_SHARED, dev_name(&pdev->dev), mc); + if (err) + return -ENODEV; + + platform_set_drvdata(pdev, mc); + + intmask = MC_INT_INVALID_GART_PAGE | + MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION; + mc_writel(mc, intmask, MC_INTMASK); + return 0; +} + +static struct platform_driver tegra20_mc_driver = { + .probe = tegra20_mc_probe, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = tegra20_mc_of_match, + }, +}; +module_platform_driver(tegra20_mc_driver); + +MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); +MODULE_DESCRIPTION("Tegra20 MC driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/drivers/memory/tegra30-mc.c b/drivers/memory/tegra30-mc.c new file mode 100644 index 000000000000..e56ff04eb5cc --- /dev/null +++ b/drivers/memory/tegra30-mc.c @@ -0,0 +1,382 @@ +/* + * Tegra30 Memory Controller + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/ratelimit.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/io.h> + +#define DRV_NAME "tegra30-mc" + +#define MC_INTSTATUS 0x0 +#define MC_INTMASK 0x4 + +#define MC_INT_ERR_SHIFT 6 +#define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT) +#define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT) +#define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2) +#define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3) +#define MC_INT_INVALID_SMMU_PAGE BIT(MC_INT_ERR_SHIFT + 4) + +#define MC_ERR_STATUS 0x8 +#define MC_ERR_ADR 0xc + +#define MC_ERR_TYPE_SHIFT 28 +#define MC_ERR_TYPE_MASK (7 << MC_ERR_TYPE_SHIFT) +#define MC_ERR_TYPE_DECERR_EMEM 2 +#define MC_ERR_TYPE_SECURITY_TRUSTZONE 3 +#define MC_ERR_TYPE_SECURITY_CARVEOUT 4 +#define MC_ERR_TYPE_INVALID_SMMU_PAGE 6 + +#define MC_ERR_INVALID_SMMU_PAGE_SHIFT 25 +#define MC_ERR_INVALID_SMMU_PAGE_MASK (7 << MC_ERR_INVALID_SMMU_PAGE_SHIFT) +#define MC_ERR_RW_SHIFT 16 +#define MC_ERR_RW BIT(MC_ERR_RW_SHIFT) +#define MC_ERR_SECURITY BIT(MC_ERR_RW_SHIFT + 1) + +#define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */ + +#define MC_EMEM_ARB_CFG 0x90 +#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 +#define MC_EMEM_ARB_TIMING_RCD 0x98 +#define MC_EMEM_ARB_TIMING_RP 0x9c +#define MC_EMEM_ARB_TIMING_RC 0xa0 +#define MC_EMEM_ARB_TIMING_RAS 0xa4 +#define MC_EMEM_ARB_TIMING_FAW 0xa8 +#define MC_EMEM_ARB_TIMING_RRD 0xac +#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 +#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 +#define MC_EMEM_ARB_TIMING_R2R 0xb8 +#define MC_EMEM_ARB_TIMING_W2W 0xbc +#define MC_EMEM_ARB_TIMING_R2W 0xc0 +#define MC_EMEM_ARB_TIMING_W2R 0xc4 + +#define MC_EMEM_ARB_DA_TURNS 0xd0 +#define MC_EMEM_ARB_DA_COVERS 0xd4 +#define MC_EMEM_ARB_MISC0 0xd8 +#define MC_EMEM_ARB_MISC1 0xdc + +#define MC_EMEM_ARB_RING3_THROTTLE 0xe4 +#define MC_EMEM_ARB_OVERRIDE 0xe8 + +#define MC_TIMING_CONTROL 0xfc + +#define MC_CLIENT_ID_MASK 0x7f + +#define NUM_MC_REG_BANKS 4 + +struct tegra30_mc { + void __iomem *regs[NUM_MC_REG_BANKS]; + struct device *dev; + u32 ctx[0]; +}; + +static inline u32 mc_readl(struct tegra30_mc *mc, u32 offs) +{ + u32 val = 0; + + if (offs < 0x10) + val = readl(mc->regs[0] + offs); + if (offs < 0x1f0) + val = readl(mc->regs[1] + offs - 0x3c); + if (offs < 0x228) + val = readl(mc->regs[2] + offs - 0x200); + if (offs < 0x400) + val = readl(mc->regs[3] + offs - 0x284); + + return val; +} + +static inline void mc_writel(struct tegra30_mc *mc, u32 val, u32 offs) +{ + if (offs < 0x10) { + writel(val, mc->regs[0] + offs); + return; + } + if (offs < 0x1f0) { + writel(val, mc->regs[1] + offs - 0x3c); + return; + } + if (offs < 0x228) { + writel(val, mc->regs[2] + offs - 0x200); + return; + } + if (offs < 0x400) { + writel(val, mc->regs[3] + offs - 0x284); + return; + } +} + +static const char * const tegra30_mc_client[] = { + "csr_ptcr", + "cbr_display0a", + "cbr_display0ab", + "cbr_display0b", + "cbr_display0bb", + "cbr_display0c", + "cbr_display0cb", + "cbr_display1b", + "cbr_display1bb", + "cbr_eppup", + "cbr_g2pr", + "cbr_g2sr", + "cbr_mpeunifbr", + "cbr_viruv", + "csr_afir", + "csr_avpcarm7r", + "csr_displayhc", + "csr_displayhcb", + "csr_fdcdrd", + "csr_fdcdrd2", + "csr_g2dr", + "csr_hdar", + "csr_host1xdmar", + "csr_host1xr", + "csr_idxsrd", + "csr_idxsrd2", + "csr_mpe_ipred", + "csr_mpeamemrd", + "csr_mpecsrd", + "csr_ppcsahbdmar", + "csr_ppcsahbslvr", + "csr_satar", + "csr_texsrd", + "csr_texsrd2", + "csr_vdebsevr", + "csr_vdember", + "csr_vdemcer", + "csr_vdetper", + "csr_mpcorelpr", + "csr_mpcorer", + "cbw_eppu", + "cbw_eppv", + "cbw_eppy", + "cbw_mpeunifbw", + "cbw_viwsb", + "cbw_viwu", + "cbw_viwv", + "cbw_viwy", + "ccw_g2dw", + "csw_afiw", + "csw_avpcarm7w", + "csw_fdcdwr", + "csw_fdcdwr2", + "csw_hdaw", + "csw_host1xw", + "csw_ispw", + "csw_mpcorelpw", + "csw_mpcorew", + "csw_mpecswr", + "csw_ppcsahbdmaw", + "csw_ppcsahbslvw", + "csw_sataw", + "csw_vdebsevw", + "csw_vdedbgw", + "csw_vdembew", + "csw_vdetpmw", +}; + +static void tegra30_mc_decode(struct tegra30_mc *mc, int n) +{ + u32 err, addr; + const char * const mc_int_err[] = { + "MC_DECERR", + "Unknown", + "MC_SECURITY_ERR", + "MC_ARBITRATION_EMEM", + "MC_SMMU_ERR", + }; + const char * const err_type[] = { + "Unknown", + "Unknown", + "DECERR_EMEM", + "SECURITY_TRUSTZONE", + "SECURITY_CARVEOUT", + "Unknown", + "INVALID_SMMU_PAGE", + "Unknown", + }; + char attr[6]; + int cid, perm, type, idx; + const char *client = "Unknown"; + + idx = n - MC_INT_ERR_SHIFT; + if ((idx < 0) || (idx >= ARRAY_SIZE(mc_int_err)) || (idx == 1)) { + dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n", + BIT(n)); + return; + } + + err = readl(mc + MC_ERR_STATUS); + + type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT; + perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >> + MC_ERR_INVALID_SMMU_PAGE_SHIFT; + if (type == MC_ERR_TYPE_INVALID_SMMU_PAGE) + sprintf(attr, "%c-%c-%c", + (perm & BIT(2)) ? 'R' : '-', + (perm & BIT(1)) ? 'W' : '-', + (perm & BIT(0)) ? 'S' : '-'); + else + attr[0] = '\0'; + + cid = err & MC_CLIENT_ID_MASK; + if (cid < ARRAY_SIZE(tegra30_mc_client)) + client = tegra30_mc_client[cid]; + + addr = readl(mc + MC_ERR_ADR); + + dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n", + mc_int_err[idx], err, addr, client, + (err & MC_ERR_SECURITY) ? "secure" : "non-secure", + (err & MC_ERR_RW) ? "write" : "read", + err_type[type], attr); +} + +static const u32 tegra30_mc_ctx[] = { + MC_EMEM_ARB_CFG, + MC_EMEM_ARB_OUTSTANDING_REQ, + MC_EMEM_ARB_TIMING_RCD, + MC_EMEM_ARB_TIMING_RP, + MC_EMEM_ARB_TIMING_RC, + MC_EMEM_ARB_TIMING_RAS, + MC_EMEM_ARB_TIMING_FAW, + MC_EMEM_ARB_TIMING_RRD, + MC_EMEM_ARB_TIMING_RAP2PRE, + MC_EMEM_ARB_TIMING_WAP2PRE, + MC_EMEM_ARB_TIMING_R2R, + MC_EMEM_ARB_TIMING_W2W, + MC_EMEM_ARB_TIMING_R2W, + MC_EMEM_ARB_TIMING_W2R, + MC_EMEM_ARB_DA_TURNS, + MC_EMEM_ARB_DA_COVERS, + MC_EMEM_ARB_MISC0, + MC_EMEM_ARB_MISC1, + MC_EMEM_ARB_RING3_THROTTLE, + MC_EMEM_ARB_OVERRIDE, + MC_INTMASK, +}; + +static int tegra30_mc_suspend(struct device *dev) +{ + int i; + struct tegra30_mc *mc = dev_get_drvdata(dev); + + for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++) + mc->ctx[i] = mc_readl(mc, tegra30_mc_ctx[i]); + return 0; +} + +static int tegra30_mc_resume(struct device *dev) +{ + int i; + struct tegra30_mc *mc = dev_get_drvdata(dev); + + for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++) + mc_writel(mc, mc->ctx[i], tegra30_mc_ctx[i]); + + mc_writel(mc, 1, MC_TIMING_CONTROL); + /* Read-back to ensure that write reached */ + mc_readl(mc, MC_TIMING_CONTROL); + return 0; +} + +static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm, + tegra30_mc_suspend, + tegra30_mc_resume, NULL); + +static const struct of_device_id tegra30_mc_of_match[] __devinitconst = { + { .compatible = "nvidia,tegra30-mc", }, + {}, +}; + +static irqreturn_t tegra30_mc_isr(int irq, void *data) +{ + u32 stat, mask, bit; + struct tegra30_mc *mc = data; + + stat = mc_readl(mc, MC_INTSTATUS); + mask = mc_readl(mc, MC_INTMASK); + mask &= stat; + if (!mask) + return IRQ_NONE; + while ((bit = ffs(mask)) != 0) + tegra30_mc_decode(mc, bit - 1); + mc_writel(mc, stat, MC_INTSTATUS); + return IRQ_HANDLED; +} + +static int __devinit tegra30_mc_probe(struct platform_device *pdev) +{ + struct resource *irq; + struct tegra30_mc *mc; + size_t bytes; + int err, i; + u32 intmask; + + bytes = sizeof(*mc) + sizeof(u32) * ARRAY_SIZE(tegra30_mc_ctx); + mc = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL); + if (!mc) + return -ENOMEM; + mc->dev = &pdev->dev; + + for (i = 0; i < ARRAY_SIZE(mc->regs); i++) { + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) + return -ENODEV; + mc->regs[i] = devm_request_and_ioremap(&pdev->dev, res); + if (!mc->regs[i]) + return -EBUSY; + } + + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!irq) + return -ENODEV; + err = devm_request_irq(&pdev->dev, irq->start, tegra30_mc_isr, + IRQF_SHARED, dev_name(&pdev->dev), mc); + if (err) + return -ENODEV; + + platform_set_drvdata(pdev, mc); + + intmask = MC_INT_INVALID_SMMU_PAGE | + MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION; + mc_writel(mc, intmask, MC_INTMASK); + return 0; +} + +static struct platform_driver tegra30_mc_driver = { + .probe = tegra30_mc_probe, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = tegra30_mc_of_match, + .pm = &tegra30_mc_pm, + }, +}; +module_platform_driver(tegra30_mc_driver); + +MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); +MODULE_DESCRIPTION("Tegra30 MC driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 968469555956..757fbd0f2a14 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -508,14 +508,6 @@ config USB_SWITCH_FSA9480 stereo and mono audio, video, microphone and UART data to use a common connector port. -config MAX8997_MUIC - tristate "MAX8997 MUIC Support" - depends on MFD_MAX8997 - help - If you say yes here you get support for the MUIC device of - Maxim MAX8997 PMIC. - The MAX8997 MUIC is a USB port accessory detector and switch. - source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 509d0569dc04..162861788c6d 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -50,4 +50,3 @@ obj-y += lis3lv02d/ obj-y += carma/ obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/ -obj-$(CONFIG_MAX8997_MUIC) += max8997-muic.o diff --git a/drivers/parport/parport_pc.c b/drivers/parport/parport_pc.c index 402956321d33..5abffe58a9d2 100644 --- a/drivers/parport/parport_pc.c +++ b/drivers/parport/parport_pc.c @@ -2075,7 +2075,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); if (p->base_hi && priv->ecr) - printk(" (0x%lx)", p->base_hi); + printk(KERN_CONT " (0x%lx)", p->base_hi); if (p->irq == PARPORT_IRQ_AUTO) { p->irq = PARPORT_IRQ_NONE; parport_irq_probe(p); @@ -2086,7 +2086,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, p->irq = PARPORT_IRQ_NONE; } if (p->irq != PARPORT_IRQ_NONE) { - printk(", irq %d", p->irq); + printk(KERN_CONT ", irq %d", p->irq); priv->ctr_writable |= 0x10; if (p->dma == PARPORT_DMA_AUTO) { @@ -2110,21 +2110,21 @@ struct parport *parport_pc_probe_port(unsigned long int base, /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ #endif /* IEEE 1284 support */ if (p->dma != PARPORT_DMA_NONE) { - printk(", dma %d", p->dma); + printk(KERN_CONT ", dma %d", p->dma); p->modes |= PARPORT_MODE_DMA; } else - printk(", using FIFO"); + printk(KERN_CONT ", using FIFO"); } else /* We can't use the DMA channel after all. */ p->dma = PARPORT_DMA_NONE; #endif /* Allowed to use FIFO/DMA */ - printk(" ["); + printk(KERN_CONT " ["); #define printmode(x) \ {\ if (p->modes & PARPORT_MODE_##x) {\ - printk("%s%s", f ? "," : "", #x);\ + printk(KERN_CONT "%s%s", f ? "," : "", #x);\ f++;\ } \ } @@ -2140,9 +2140,9 @@ struct parport *parport_pc_probe_port(unsigned long int base, } #undef printmode #ifndef CONFIG_PARPORT_1284 - printk("(,...)"); + printk(KERN_CONT "(,...)"); #endif /* CONFIG_PARPORT_1284 */ - printk("]\n"); + printk(KERN_CONT "]\n"); if (probedirq != PARPORT_IRQ_NONE) printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); diff --git a/drivers/staging/android/Kconfig b/drivers/staging/android/Kconfig index eb1dee26bda3..c706635f3f82 100644 --- a/drivers/staging/android/Kconfig +++ b/drivers/staging/android/Kconfig @@ -53,8 +53,6 @@ config ANDROID_LOW_MEMORY_KILLER ---help--- Register processes to be killed when memory is low -source "drivers/staging/android/switch/Kconfig" - config ANDROID_INTF_ALARM bool "Android alarm driver" depends on RTC_CLASS @@ -80,7 +78,6 @@ config ANDROID_ALARM_OLDDRV_COMPAT Provides preprocessor alias to aid compatability with older out-of-tree drivers that use the Android Alarm in-kernel API. This will be removed eventually. - endif # if ANDROID endmenu diff --git a/drivers/staging/android/Makefile b/drivers/staging/android/Makefile index 9b6c9ed91f69..045d17bde524 100644 --- a/drivers/staging/android/Makefile +++ b/drivers/staging/android/Makefile @@ -6,6 +6,5 @@ obj-$(CONFIG_ANDROID_RAM_CONSOLE) += ram_console.o obj-$(CONFIG_ANDROID_TIMED_OUTPUT) += timed_output.o obj-$(CONFIG_ANDROID_TIMED_GPIO) += timed_gpio.o obj-$(CONFIG_ANDROID_LOW_MEMORY_KILLER) += lowmemorykiller.o -obj-$(CONFIG_ANDROID_SWITCH) += switch/ obj-$(CONFIG_ANDROID_INTF_ALARM) += alarm.o obj-$(CONFIG_ANDROID_INTF_ALARM_DEV) += alarm-dev.o diff --git a/drivers/staging/android/switch/Kconfig b/drivers/staging/android/switch/Kconfig deleted file mode 100644 index 36846f62f4bc..000000000000 --- a/drivers/staging/android/switch/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -menuconfig ANDROID_SWITCH - tristate "Android Switch class support" - help - Say Y here to enable Android switch class support. This allows - monitoring switches by userspace via sysfs and uevent. - -config ANDROID_SWITCH_GPIO - tristate "Android GPIO Switch support" - depends on GENERIC_GPIO && ANDROID_SWITCH - help - Say Y here to enable GPIO based switch support. diff --git a/drivers/staging/android/switch/Makefile b/drivers/staging/android/switch/Makefile deleted file mode 100644 index d76bfdcedfaf..000000000000 --- a/drivers/staging/android/switch/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# Android Switch Class Driver -obj-$(CONFIG_ANDROID_SWITCH) += switch_class.o -obj-$(CONFIG_ANDROID_SWITCH_GPIO) += switch_gpio.o - diff --git a/drivers/staging/android/switch/switch.h b/drivers/staging/android/switch/switch.h deleted file mode 100644 index 4fcb3109875a..000000000000 --- a/drivers/staging/android/switch/switch.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Switch class driver - * - * Copyright (C) 2008 Google, Inc. - * Author: Mike Lockwood <lockwood@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * -*/ - -#ifndef __LINUX_SWITCH_H__ -#define __LINUX_SWITCH_H__ - -struct switch_dev { - const char *name; - struct device *dev; - int index; - int state; - - ssize_t (*print_name)(struct switch_dev *sdev, char *buf); - ssize_t (*print_state)(struct switch_dev *sdev, char *buf); -}; - -struct gpio_switch_platform_data { - const char *name; - unsigned gpio; - - /* if NULL, switch_dev.name will be printed */ - const char *name_on; - const char *name_off; - /* if NULL, "0" or "1" will be printed */ - const char *state_on; - const char *state_off; -}; - -extern int switch_dev_register(struct switch_dev *sdev); -extern void switch_dev_unregister(struct switch_dev *sdev); - -static inline int switch_get_state(struct switch_dev *sdev) -{ - return sdev->state; -} - -extern void switch_set_state(struct switch_dev *sdev, int state); - -#endif /* __LINUX_SWITCH_H__ */ diff --git a/drivers/staging/android/switch/switch_class.c b/drivers/staging/android/switch/switch_class.c deleted file mode 100644 index 74680446fc66..000000000000 --- a/drivers/staging/android/switch/switch_class.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * switch_class.c - * - * Copyright (C) 2008 Google, Inc. - * Author: Mike Lockwood <lockwood@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * -*/ - -#include <linux/module.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/fs.h> -#include <linux/err.h> -#include "switch.h" - -struct class *switch_class; -static atomic_t device_count; - -static ssize_t state_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct switch_dev *sdev = (struct switch_dev *) - dev_get_drvdata(dev); - - if (sdev->print_state) { - int ret = sdev->print_state(sdev, buf); - if (ret >= 0) - return ret; - } - return sprintf(buf, "%d\n", sdev->state); -} - -static ssize_t name_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct switch_dev *sdev = (struct switch_dev *) - dev_get_drvdata(dev); - - if (sdev->print_name) { - int ret = sdev->print_name(sdev, buf); - if (ret >= 0) - return ret; - } - return sprintf(buf, "%s\n", sdev->name); -} - -static DEVICE_ATTR(state, S_IRUGO | S_IWUSR, state_show, NULL); -static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, name_show, NULL); - -void switch_set_state(struct switch_dev *sdev, int state) -{ - char name_buf[120]; - char state_buf[120]; - char *prop_buf; - char *envp[3]; - int env_offset = 0; - int length; - - if (sdev->state != state) { - sdev->state = state; - - prop_buf = (char *)get_zeroed_page(GFP_KERNEL); - if (prop_buf) { - length = name_show(sdev->dev, NULL, prop_buf); - if (length > 0) { - if (prop_buf[length - 1] == '\n') - prop_buf[length - 1] = 0; - snprintf(name_buf, sizeof(name_buf), - "SWITCH_NAME=%s", prop_buf); - envp[env_offset++] = name_buf; - } - length = state_show(sdev->dev, NULL, prop_buf); - if (length > 0) { - if (prop_buf[length - 1] == '\n') - prop_buf[length - 1] = 0; - snprintf(state_buf, sizeof(state_buf), - "SWITCH_STATE=%s", prop_buf); - envp[env_offset++] = state_buf; - } - envp[env_offset] = NULL; - kobject_uevent_env(&sdev->dev->kobj, KOBJ_CHANGE, envp); - free_page((unsigned long)prop_buf); - } else { - printk(KERN_ERR "out of memory in switch_set_state\n"); - kobject_uevent(&sdev->dev->kobj, KOBJ_CHANGE); - } - } -} -EXPORT_SYMBOL_GPL(switch_set_state); - -static int create_switch_class(void) -{ - if (!switch_class) { - switch_class = class_create(THIS_MODULE, "switch"); - if (IS_ERR(switch_class)) - return PTR_ERR(switch_class); - atomic_set(&device_count, 0); - } - - return 0; -} - -int switch_dev_register(struct switch_dev *sdev) -{ - int ret; - - if (!switch_class) { - ret = create_switch_class(); - if (ret < 0) - return ret; - } - - sdev->index = atomic_inc_return(&device_count); - sdev->dev = device_create(switch_class, NULL, - MKDEV(0, sdev->index), NULL, sdev->name); - if (IS_ERR(sdev->dev)) - return PTR_ERR(sdev->dev); - - ret = device_create_file(sdev->dev, &dev_attr_state); - if (ret < 0) - goto err_create_file_1; - ret = device_create_file(sdev->dev, &dev_attr_name); - if (ret < 0) - goto err_create_file_2; - - dev_set_drvdata(sdev->dev, sdev); - sdev->state = 0; - return 0; - -err_create_file_2: - device_remove_file(sdev->dev, &dev_attr_state); -err_create_file_1: - device_destroy(switch_class, MKDEV(0, sdev->index)); - printk(KERN_ERR "switch: Failed to register driver %s\n", sdev->name); - - return ret; -} -EXPORT_SYMBOL_GPL(switch_dev_register); - -void switch_dev_unregister(struct switch_dev *sdev) -{ - device_remove_file(sdev->dev, &dev_attr_name); - device_remove_file(sdev->dev, &dev_attr_state); - device_destroy(switch_class, MKDEV(0, sdev->index)); - dev_set_drvdata(sdev->dev, NULL); -} -EXPORT_SYMBOL_GPL(switch_dev_unregister); - -static int __init switch_class_init(void) -{ - return create_switch_class(); -} - -static void __exit switch_class_exit(void) -{ - class_destroy(switch_class); -} - -module_init(switch_class_init); -module_exit(switch_class_exit); - -MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>"); -MODULE_DESCRIPTION("Switch class driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/staging/android/switch/switch_gpio.c b/drivers/staging/android/switch/switch_gpio.c deleted file mode 100644 index 38b2c2f6004e..000000000000 --- a/drivers/staging/android/switch/switch_gpio.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * switch_gpio.c - * - * Copyright (C) 2008 Google, Inc. - * Author: Mike Lockwood <lockwood@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * -*/ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/workqueue.h> -#include <linux/gpio.h> -#include "switch.h" - -struct gpio_switch_data { - struct switch_dev sdev; - unsigned gpio; - const char *name_on; - const char *name_off; - const char *state_on; - const char *state_off; - int irq; - struct work_struct work; -}; - -static void gpio_switch_work(struct work_struct *work) -{ - int state; - struct gpio_switch_data *data = - container_of(work, struct gpio_switch_data, work); - - state = gpio_get_value(data->gpio); - switch_set_state(&data->sdev, state); -} - -static irqreturn_t gpio_irq_handler(int irq, void *dev_id) -{ - struct gpio_switch_data *switch_data = - (struct gpio_switch_data *)dev_id; - - schedule_work(&switch_data->work); - return IRQ_HANDLED; -} - -static ssize_t switch_gpio_print_state(struct switch_dev *sdev, char *buf) -{ - struct gpio_switch_data *switch_data = - container_of(sdev, struct gpio_switch_data, sdev); - const char *state; - if (switch_get_state(sdev)) - state = switch_data->state_on; - else - state = switch_data->state_off; - - if (state) - return sprintf(buf, "%s\n", state); - return -1; -} - -static int gpio_switch_probe(struct platform_device *pdev) -{ - struct gpio_switch_platform_data *pdata = pdev->dev.platform_data; - struct gpio_switch_data *switch_data; - int ret = 0; - - if (!pdata) - return -EBUSY; - - switch_data = kzalloc(sizeof(struct gpio_switch_data), GFP_KERNEL); - if (!switch_data) - return -ENOMEM; - - switch_data->sdev.name = pdata->name; - switch_data->gpio = pdata->gpio; - switch_data->name_on = pdata->name_on; - switch_data->name_off = pdata->name_off; - switch_data->state_on = pdata->state_on; - switch_data->state_off = pdata->state_off; - switch_data->sdev.print_state = switch_gpio_print_state; - - ret = switch_dev_register(&switch_data->sdev); - if (ret < 0) - goto err_switch_dev_register; - - ret = gpio_request(switch_data->gpio, pdev->name); - if (ret < 0) - goto err_request_gpio; - - ret = gpio_direction_input(switch_data->gpio); - if (ret < 0) - goto err_set_gpio_input; - - INIT_WORK(&switch_data->work, gpio_switch_work); - - switch_data->irq = gpio_to_irq(switch_data->gpio); - if (switch_data->irq < 0) { - ret = switch_data->irq; - goto err_detect_irq_num_failed; - } - - ret = request_irq(switch_data->irq, gpio_irq_handler, - IRQF_TRIGGER_LOW, pdev->name, switch_data); - if (ret < 0) - goto err_request_irq; - - /* Perform initial detection */ - gpio_switch_work(&switch_data->work); - - return 0; - -err_request_irq: -err_detect_irq_num_failed: -err_set_gpio_input: - gpio_free(switch_data->gpio); -err_request_gpio: - switch_dev_unregister(&switch_data->sdev); -err_switch_dev_register: - kfree(switch_data); - - return ret; -} - -static int __devexit gpio_switch_remove(struct platform_device *pdev) -{ - struct gpio_switch_data *switch_data = platform_get_drvdata(pdev); - - cancel_work_sync(&switch_data->work); - gpio_free(switch_data->gpio); - switch_dev_unregister(&switch_data->sdev); - kfree(switch_data); - - return 0; -} - -static struct platform_driver gpio_switch_driver = { - .probe = gpio_switch_probe, - .remove = __devexit_p(gpio_switch_remove), - .driver = { - .name = "switch-gpio", - .owner = THIS_MODULE, - }, -}; - -static int __init gpio_switch_init(void) -{ - return platform_driver_register(&gpio_switch_driver); -} - -static void __exit gpio_switch_exit(void) -{ - platform_driver_unregister(&gpio_switch_driver); -} - -module_init(gpio_switch_init); -module_exit(gpio_switch_exit); - -MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>"); -MODULE_DESCRIPTION("GPIO Switch driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/uio/uio_pdrv_genirq.c b/drivers/uio/uio_pdrv_genirq.c index b98371d93a92..42202cd83158 100644 --- a/drivers/uio/uio_pdrv_genirq.c +++ b/drivers/uio/uio_pdrv_genirq.c @@ -146,6 +146,14 @@ static int uio_pdrv_genirq_probe(struct platform_device *pdev) priv->flags = 0; /* interrupt is enabled to begin with */ priv->pdev = pdev; + if (!uioinfo->irq) { + ret = platform_get_irq(pdev, 0); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get IRQ\n"); + goto bad0; + } + uioinfo->irq = ret; + } uiomem = &uioinfo->mem[0]; for (i = 0; i < pdev->num_resources; ++i) { diff --git a/drivers/usb/core/sysfs.c b/drivers/usb/core/sysfs.c index 566d9f94f735..9a56e3adf476 100644 --- a/drivers/usb/core/sysfs.c +++ b/drivers/usb/core/sysfs.c @@ -73,7 +73,7 @@ set_bConfigurationValue(struct device *dev, struct device_attribute *attr, return (value < 0) ? value : count; } -static DEVICE_ATTR(bConfigurationValue, S_IRUGO | S_IWUSR, +static DEVICE_ATTR_IGNORE_LOCKDEP(bConfigurationValue, S_IRUGO | S_IWUSR, show_bConfigurationValue, set_bConfigurationValue); /* String fields */ @@ -595,7 +595,7 @@ static ssize_t usb_dev_authorized_store(struct device *dev, return result < 0? result : size; } -static DEVICE_ATTR(authorized, 0644, +static DEVICE_ATTR_IGNORE_LOCKDEP(authorized, 0644, usb_dev_authorized_show, usb_dev_authorized_store); /* "Safely remove a device" */ @@ -618,7 +618,7 @@ static ssize_t usb_remove_store(struct device *dev, usb_unlock_device(udev); return rc; } -static DEVICE_ATTR(remove, 0200, NULL, usb_remove_store); +static DEVICE_ATTR_IGNORE_LOCKDEP(remove, 0200, NULL, usb_remove_store); static struct attribute *dev_attrs[] = { diff --git a/drivers/w1/slaves/w1_ds2408.c b/drivers/w1/slaves/w1_ds2408.c index 7c8cdb8aed26..8e813eed0f0a 100644 --- a/drivers/w1/slaves/w1_ds2408.c +++ b/drivers/w1/slaves/w1_ds2408.c @@ -332,7 +332,6 @@ static struct bin_attribute w1_f29_sysfs_bin_files[NB_SYSFS_BIN_FILES] = { }, .size = 1, .read = w1_f29_read_cond_search_mask, - .write = 0, }, { .attr = { @@ -341,7 +340,6 @@ static struct bin_attribute w1_f29_sysfs_bin_files[NB_SYSFS_BIN_FILES] = { }, .size = 1, .read = w1_f29_read_cond_search_polarity, - .write = 0, }, { .attr = { diff --git a/drivers/w1/w1.c b/drivers/w1/w1.c index 9761950697b4..2f2e894ea0c8 100644 --- a/drivers/w1/w1.c +++ b/drivers/w1/w1.c @@ -1027,7 +1027,7 @@ static int __init w1_init(void) retval = driver_register(&w1_slave_driver); if (retval) { printk(KERN_ERR - "Failed to register master driver. err=%d.\n", + "Failed to register slave driver. err=%d.\n", retval); goto err_out_master_unregister; } diff --git a/drivers/w1/w1_io.c b/drivers/w1/w1_io.c index 3135b2c63998..e10acc237733 100644 --- a/drivers/w1/w1_io.c +++ b/drivers/w1/w1_io.c @@ -31,6 +31,9 @@ static int w1_delay_parm = 1; module_param_named(delay_coef, w1_delay_parm, int, 0); +static int w1_disable_irqs = 0; +module_param_named(disable_irqs, w1_disable_irqs, int, 0); + static u8 w1_crc8_table[] = { 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65, 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220, @@ -79,6 +82,10 @@ static u8 w1_touch_bit(struct w1_master *dev, int bit) */ static void w1_write_bit(struct w1_master *dev, int bit) { + unsigned long flags = 0; + + if(w1_disable_irqs) local_irq_save(flags); + if (bit) { dev->bus_master->write_bit(dev->bus_master->data, 0); w1_delay(6); @@ -90,6 +97,8 @@ static void w1_write_bit(struct w1_master *dev, int bit) dev->bus_master->write_bit(dev->bus_master->data, 1); w1_delay(10); } + + if(w1_disable_irqs) local_irq_restore(flags); } /** @@ -158,7 +167,7 @@ EXPORT_SYMBOL_GPL(w1_write_8); static u8 w1_read_bit(struct w1_master *dev) { int result; - unsigned long flags; + unsigned long flags = 0; /* sample timing is critical here */ local_irq_save(flags); @@ -318,6 +327,9 @@ EXPORT_SYMBOL_GPL(w1_read_block); int w1_reset_bus(struct w1_master *dev) { int result; + unsigned long flags = 0; + + if(w1_disable_irqs) local_irq_save(flags); if (dev->bus_master->reset_bus) result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1; @@ -330,19 +342,21 @@ int w1_reset_bus(struct w1_master *dev) * cpu for such a short amount of time AND get it back in * the maximum amount of time. */ - w1_delay(480); + w1_delay(500); dev->bus_master->write_bit(dev->bus_master->data, 1); w1_delay(70); result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1; - /* minmum 70 (above) + 410 = 480 us + /* minmum 70 (above) + 430 = 500 us * There aren't any timing requirements between a reset and * the following transactions. Sleeping is safe here. */ - /* w1_delay(410); min required time */ + /* w1_delay(430); min required time */ msleep(1); } + if(w1_disable_irqs) local_irq_restore(flags); + return result; } EXPORT_SYMBOL_GPL(w1_reset_bus); |