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| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-06-08 06:08:16 +0300 |
|---|---|---|
| committer | samin <samin.guo@starfivetech.com> | 2022-06-08 14:30:24 +0300 |
| commit | f9ee1898eccb5ac0b164a4d6c7a06bf002d23c0e (patch) | |
| tree | 3bf14a2f55ba8da2d05d2e3f46ebd3853ec6671c /drivers/usb/cdns3/cdns3-debug.h | |
| parent | 303ba87f4ec10c5bb8b4b087a1087a51966a8972 (diff) | |
| download | linux-f9ee1898eccb5ac0b164a4d6c7a06bf002d23c0e.tar.xz | |
clk:starfive:jh7110: Change uart3-uart5 clk register info
The core_clk division register of uart3-uart5 include fractional and
integral parts,but now only use the integral part,so include shift
operation. The integral part include 8 bit,so the max value can be
configed is 255.In order to support 115200 bandrate,so limit the max
value to 10.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'drivers/usb/cdns3/cdns3-debug.h')
0 files changed, 0 insertions, 0 deletions