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| author | Frank Li <Frank.Li@nxp.com> | 2024-03-22 19:47:05 +0300 | 
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2024-04-02 13:55:44 +0300 | 
| commit | c6ddd6e7b166532a0816825442ff60f70aed9647 (patch) | |
| tree | 9007f1c44273970382ad0f81b7c9d64cc9d52611 /drivers/usb/cdns3/cdns3-debug.h | |
| parent | 6f8e0aca838e163e81fde176e945161d50679339 (diff) | |
| download | linux-c6ddd6e7b166532a0816825442ff60f70aed9647.tar.xz | |
arm64: dts: imx8-ss-conn: fix usdhc wrong lpcg clock order
The actual clock show wrong frequency:
   echo on >/sys/devices/platform/bus\@5b000000/5b010000.mmc/power/control
   cat /sys/kernel/debug/mmc0/ios
   clock:          200000000 Hz
   actual clock:   166000000 Hz
                   ^^^^^^^^^
   .....
According to
sdhc0_lpcg: clock-controller@5b200000 {
                compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5b200000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
                         <&conn_ipg_clk>, <&conn_axi_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
                                <IMX_LPCG_CLK_5>;
                clock-output-names = "sdhc0_lpcg_per_clk",
                                     "sdhc0_lpcg_ipg_clk",
                                     "sdhc0_lpcg_ahb_clk";
                power-domains = <&pd IMX_SC_R_SDHC_0>;
        }
"per_clk" should be IMX_LPCG_CLK_0 instead of IMX_LPCG_CLK_5.
After correct clocks order:
   echo on >/sys/devices/platform/bus\@5b000000/5b010000.mmc/power/control
   cat /sys/kernel/debug/mmc0/ios
   clock:          200000000 Hz
   actual clock:   198000000 Hz
                   ^^^^^^^^
   ...
Fixes: 16c4ea7501b1 ("arm64: dts: imx8: switch to new lpcg clock binding")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/usb/cdns3/cdns3-debug.h')
0 files changed, 0 insertions, 0 deletions
