reset:starfive:jh7110: Delete redundant logic

In the hardware design, the IPs RESET signal of jh7110 is divided into two groups,
one group is active high, and the other group is active low.

However, the software does not need to distinguish whether the RESET signal is active high or active low,
Write 1 to be assert, and write 0 to deassert.

Therefore, the software does not need to add additional logic to distinguish these two sets of signals.

Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>

0 files changed, 0 insertions, 0 deletions