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| author | Hugo Villeneuve <hvilleneuve@dimonoff.com> | 2024-01-18 18:22:08 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-01-28 06:05:04 +0300 |
| commit | 08ad4824f74dd64bde06f8530505ae2b663953c2 (patch) | |
| tree | 090c5501ddae475ca0f961513e145147bfc338e0 /drivers/tty/serial/max310x.c | |
| parent | e16b9c8ca378e44b92edd95743f6f0160ce616e7 (diff) | |
| download | linux-08ad4824f74dd64bde06f8530505ae2b663953c2.tar.xz | |
serial: max310x: replace hardcoded masks with preferred GENMASK()
GENMASK() is preferred when defining bitmasks.
Of all the masks changed, only MAX310x_REV_MASK is actually used.
No functional change.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Link: https://lore.kernel.org/r/20240118152213.2644269-13-hugo@hugovil.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/max310x.c')
| -rw-r--r-- | drivers/tty/serial/max310x.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c index 701bf54e4084..c93b326faf89 100644 --- a/drivers/tty/serial/max310x.c +++ b/drivers/tty/serial/max310x.c @@ -161,14 +161,14 @@ #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ /* Flow control trigger level register masks */ -#define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ -#define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ +#define MAX310X_FLOWLVL_HALT_MASK GENMASK(3, 0) /* Flow control halt level */ +#define MAX310X_FLOWLVL_RES_MASK GENMASK(7, 4) /* Flow control resume level */ #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) /* FIFO interrupt trigger level register masks */ -#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ -#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ +#define MAX310X_FIFOTRIGLVL_TX_MASK GENMASK(3, 0) /* TX FIFO trigger level */ +#define MAX310X_FIFOTRIGLVL_RX_MASK GENMASK(7, 4) /* RX FIFO trigger level */ #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) @@ -215,8 +215,8 @@ */ /* PLL configuration register masks */ -#define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ -#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ +#define MAX310X_PLLCFG_PREDIV_MASK GENMASK(5, 0) /* PLL predivision value */ +#define MAX310X_PLLCFG_PLLFACTOR_MASK GENMASK(7, 6) /* PLL multiplication factor */ /* Baud rate generator configuration register bits */ #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ @@ -235,7 +235,7 @@ /* Misc definitions */ #define MAX310X_FIFO_SIZE (128) -#define MAX310x_REV_MASK (0xf8) +#define MAX310x_REV_MASK GENMASK(7, 3) #define MAX310X_WRITE_BIT 0x80 /* MAX3107 specific */ |