diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2019-01-07 10:47:41 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-01-07 18:17:43 +0300 |
| commit | 6a130448498c151d31f1fb6f3003f5cf37b829e0 (patch) | |
| tree | d8e816e1408103401717b5e1d73b23b35dbcbb67 /drivers/spi/spi-fsl-lpspi.c | |
| parent | c23fdef891acc3891b2885f29d9f48193ecc865a (diff) | |
| download | linux-6a130448498c151d31f1fb6f3003f5cf37b829e0.tar.xz | |
spi: lpspi: Fix wrong transmission when don't use CONT
Add judgment on SR_MBF and FSR_RXCOUNT.
In PIO mode, if don't use CONT to keep cs selected in one transfer, the
transfer will go wrong. FCIE will be set after one frame transfer
finish. If use CONT, the frame refer to the whole data in one transfer.
If don't use CONT, the frame refer to one byte of whole data. This will
cause the transfer ending early.
This patch add a register reading in isr function, it might lead to a
slight decrease in the max transmission speed in PIO mode.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-fsl-lpspi.c')
| -rw-r--r-- | drivers/spi/spi-fsl-lpspi.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index ba207931e209..d0b2d551cc43 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -48,6 +48,7 @@ #define CR_RTF BIT(8) #define CR_RST BIT(1) #define CR_MEN BIT(0) +#define SR_MBF BIT(24) #define SR_TCF BIT(10) #define SR_FCF BIT(9) #define SR_RDF BIT(1) @@ -61,6 +62,7 @@ #define CFGR1_PCSPOL BIT(8) #define CFGR1_NOSTALL BIT(3) #define CFGR1_MASTER BIT(0) +#define FSR_RXCOUNT (BIT(16)|BIT(17)|BIT(18)) #define RSR_RXEMPTY BIT(1) #define TCR_CPOL BIT(31) #define TCR_CPHA BIT(30) @@ -433,6 +435,13 @@ static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id) return IRQ_HANDLED; } + if (temp_SR & SR_MBF || + readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) { + writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); + fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); + return IRQ_HANDLED; + } + if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) { writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); complete(&fsl_lpspi->xfer_done); |