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authorXiaofei Tan <tanxiaofei@huawei.com>2018-07-18 17:14:32 +0300
committerMartin K. Petersen <martin.petersen@oracle.com>2018-07-20 04:57:40 +0300
commit1c09b663168bb5fd8562234976b76115f2aebe91 (patch)
tree30bf000df9f25ff678abbe32a6569ea07f0c8e0a /drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
parent6cca51ee0aa2540d648ff8698c3889330d897f27 (diff)
downloadlinux-1c09b663168bb5fd8562234976b76115f2aebe91.tar.xz
scsi: hisi_sas: add memory barrier in task delivery function
In task start delivery function, we need to add a memory barrier to prevent re-ordering of reading memory by hardware. Because the slot data is set in task prepare function and it could be running in another CPU. This patch adds an memory barrier after s->ready is read in the task start delivery function, and uses WRITE_ONCE() in the places where s->ready is set to ensure that the compiler does not re-order. Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/hisi_sas/hisi_sas_v1_hw.c')
-rw-r--r--drivers/scsi/hisi_sas/hisi_sas_v1_hw.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index 7dc68740eac9..8f60f0e04599 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -903,23 +903,28 @@ get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
static void start_delivery_v1_hw(struct hisi_sas_dq *dq)
{
struct hisi_hba *hisi_hba = dq->hisi_hba;
- struct hisi_sas_slot *s, *s1;
+ struct hisi_sas_slot *s, *s1, *s2 = NULL;
struct list_head *dq_list;
int dlvry_queue = dq->id;
- int wp, count = 0;
+ int wp;
dq_list = &dq->list;
list_for_each_entry_safe(s, s1, &dq->list, delivery) {
if (!s->ready)
break;
- count++;
- wp = (s->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
+ s2 = s;
list_del(&s->delivery);
}
- if (!count)
+ if (!s2)
return;
+ /*
+ * Ensure that memories for slots built on other CPUs is observed.
+ */
+ smp_rmb();
+ wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
+
hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
}