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| author | Li Ming <ming.li@zohomail.com> | 2024-11-29 16:28:25 +0300 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2024-12-11 00:49:14 +0300 |
| commit | 09ceba3a93450b652ae6910b6f65be99885f4437 (patch) | |
| tree | 422b4a51201c444662d8be990652f64ca17767b9 /drivers/pwm/pwm-stm32.c | |
| parent | da4d8c83358163df9a4addaeba0ef8bcb03b22e8 (diff) | |
| download | linux-09ceba3a93450b652ae6910b6f65be99885f4437.tar.xz | |
cxl/pci: Check dport->regs.rcd_pcie_cap availability before accessing
RCD Upstream Port's PCI Express Capability is a component registers
block stored in RCD Upstream Port RCRB. CXL PCI driver helps to map it
during the RCD probing, but mapping failure is allowed for component
registers blocks in CXL PCI driver.
dport->regs.rcd_pcie_cap is used to store the virtual address of the RCD
Upstream Port's PCI Express Capability, add a dport->regs.rcd_pcie_cap
checking in rcd_pcie_cap_emit() just in case user accesses a invalid
address via RCD sysfs.
Fixes: c5eaec79fa43 ("cxl/pci: Add sysfs attribute for CXL 1.1 device link status")
Signed-off-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/20241129132825.569237-1-ming.li@zohomail.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'drivers/pwm/pwm-stm32.c')
0 files changed, 0 insertions, 0 deletions