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authorRahul Rameshbabu <rrameshbabu@nvidia.com>2023-06-13 00:14:58 +0300
committerDavid S. Miller <davem@davemloft.net>2023-06-20 11:02:33 +0300
commitc066e74f34bc464bc1a077a688d7fa31a742d2d5 (patch)
treed56f2918240056b8c1ff2e61ddecc3245c711bfc /drivers/ptp/ptp_clockmatrix.h
parent67ac72a599d833ff7d9b210186a66d46c13f0a18 (diff)
downloadlinux-c066e74f34bc464bc1a077a688d7fa31a742d2d5.tar.xz
ptp: ptp_clockmatrix: Add .getmaxphase ptp_clock_info callback
Advertise the maximum offset the .adjphase callback is capable of supporting in nanoseconds for IDT ClockMatrix devices. Depend on ptp_clock_adjtime for handling out-of-range offsets. ptp_clock_adjtime returns -ERANGE instead of clamping out-of-range offsets. Cc: Richard Cochran <richardcochran@gmail.com> Cc: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ptp/ptp_clockmatrix.h')
-rw-r--r--drivers/ptp/ptp_clockmatrix.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index bf1e49409844..7c17c4f7f573 100644
--- a/drivers/ptp/ptp_clockmatrix.h
+++ b/drivers/ptp/ptp_clockmatrix.h
@@ -18,7 +18,7 @@
#define MAX_PLL (8)
#define MAX_REF_CLK (16)
-#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
+#define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L)
#define TOD_MASK_ADDR (0xFFA5)
#define DEFAULT_TOD_MASK (0x04)