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authorOndrej Jirman <megous@megous.com>2019-04-13 19:54:13 +0300
committerLinus Walleij <linus.walleij@linaro.org>2019-04-23 13:31:42 +0300
commitcc62383fcebe7f03c274462790fd912f4346304b (patch)
tree4c240ae16567212ec6d50baac257bba55c0e5da7 /drivers/pinctrl/sunxi/pinctrl-sunxi.h
parentf7275345728a0ff18a0607dd3706f2ca25dc53e0 (diff)
downloadlinux-cc62383fcebe7f03c274462790fd912f4346304b.tar.xz
pinctrl: sunxi: Support I/O bias voltage setting on H6
H6 SoC has a "pio group withstand voltage mode" register (datasheet description), that needs to be used to select either 1.8V or 3.3V I/O mode, based on what voltage is powering the respective pin banks and is thus used for I/O signals. Add support for configuring this register according to the voltage of the pin bank regulator (if enabled). This is similar to the support for I/O bias voltage setting patch for A80 and the same concerns apply. See: commit 402bfb3c1352 ("Support I/O bias voltage setting on A80") Signed-off-by: Ondrej Jirman <megous@megous.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sunxi/pinctrl-sunxi.h')
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index a62b81357136..44e30deeee38 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -95,6 +95,8 @@
#define PINCTRL_SUN7I_A20 BIT(7)
#define PINCTRL_SUN8I_R40 BIT(8)
+#define PIO_POW_MOD_SEL_REG 0x340
+
enum sunxi_desc_bias_voltage {
BIAS_VOLTAGE_NONE,
/*
@@ -102,6 +104,11 @@ enum sunxi_desc_bias_voltage {
* Pn_GRP_CONFIG registers, as seen on A80 SoC.
*/
BIAS_VOLTAGE_GRP_CONFIG,
+ /*
+ * Bias voltage is set through PIO_POW_MOD_SEL_REG
+ * register, as seen on H6 SoC, for example.
+ */
+ BIAS_VOLTAGE_PIO_POW_MODE_SEL,
};
struct sunxi_desc_function {