diff options
| author | Shiraz Hashim <shiraz.hashim@st.com> | 2012-11-07 18:37:25 +0400 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2012-11-11 22:36:04 +0400 |
| commit | 826d6ca8f955c7a902e775acef3bdbfc93695b04 (patch) | |
| tree | acfea21f3a3d52e0cfc706028394a4283fa6eb1b /drivers/pinctrl/spear/pinctrl-spear.c | |
| parent | 6bb0700bfe124f3ee245da24b5bb35152d2e6bfc (diff) | |
| download | linux-826d6ca8f955c7a902e775acef3bdbfc93695b04.tar.xz | |
pinctrl: SPEAr: Add SoC specific gpio configuration routines
Different SPEAr SoCs have different approach to configure pins as gpios. Some
configure a group of gpios with single register bit and others have one bit per
gpio pin. Only earlier one is implemented till now, this patch adds support for
later one.
Here we add callbacks to SoC specific code to configure gpios in
gpio_request_enable(). That will do additional SoC specific configuration to
enable gpio pins.
We also implement this callback for SPEAr1340 in this patch.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/spear/pinctrl-spear.c')
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear.c | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index cbca6dc66eb7..f9483ae42726 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -14,7 +14,6 @@ */ #include <linux/err.h> -#include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> @@ -29,16 +28,6 @@ #define DRIVER_NAME "spear-pinmux" -static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) -{ - return readl_relaxed(pmx->vbase + reg); -} - -static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) -{ - writel_relaxed(val, pmx->vbase + reg); -} - static void muxregs_endisable(struct spear_pmx *pmx, struct spear_muxreg *muxregs, u8 count, bool enable) { @@ -316,16 +305,25 @@ static int gpio_request_endisable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, bool enable) { struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct spear_pinctrl_machdata *machdata = pmx->machdata; struct spear_gpio_pingroup *gpio_pingroup; + /* + * Some SoC have configuration options applicable to group of pins, + * rather than a single pin. + */ gpio_pingroup = get_gpio_pingroup(pmx, offset); - if (IS_ERR(gpio_pingroup)) - return PTR_ERR(gpio_pingroup); - if (gpio_pingroup) muxregs_endisable(pmx, gpio_pingroup->muxregs, gpio_pingroup->nmuxregs, enable); + /* + * SoC may need some extra configurations, or configurations for single + * pin + */ + if (machdata->gpio_request_endisable) + machdata->gpio_request_endisable(pmx, offset, enable); + return 0; } |