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authorThomas Gleixner <tglx@linutronix.de>2019-05-27 09:55:01 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-05-30 21:26:32 +0300
commit2874c5fd284268364ece81a7bd936f3c8168e567 (patch)
tree81a787bcb5f3886d55dd56c4d583ff1e06041d77 /drivers/pinctrl/mvebu/pinctrl-orion.c
parenta912e80bd0bbfec053ccfdca625c2c760a8b08e8 (diff)
downloadlinux-2874c5fd284268364ece81a7bd936f3c8168e567.tar.xz
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/pinctrl/mvebu/pinctrl-orion.c')
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-orion.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
index 69cb4d9f0114..29bb9d8cbbb5 100644
--- a/drivers/pinctrl/mvebu/pinctrl-orion.c
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -1,13 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Orion pinctrl driver based on mvebu pinctrl core
*
* Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
* The first 16 MPP pins on Orion are easy to handle: they are
* configured through 2 consecutive registers, located at the base
* address of the MPP device.