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authorChunfeng Yun <chunfeng.yun@mediatek.com>2015-12-04 05:08:56 +0300
committerKishon Vijay Abraham I <kishon@ti.com>2015-12-20 12:51:37 +0300
commit43f53b19074e846f236ef230d1eb4b14b601e965 (patch)
tree707165c3123a659f97877f3ab8acefca7911804f /drivers/phy
parent3e46c3973cbafbd4974f7ab0d32071427afb7c1c (diff)
downloadlinux-43f53b19074e846f236ef230d1eb4b14b601e965.tar.xz
phy: phy-mt65xx-usb3: fix test fail of HS receiver sensitivity
when use the default value 8 of RG_USB20_SQTH, the HS receiver sensitivity test of HQA will fail, set it as 2 to fix up the issue. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/phy-mt65xx-usb3.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index e427c3b788ff..2afbf9f36d83 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -49,6 +49,8 @@
#define PA6_RG_U2_ISO_EN BIT(31)
#define PA6_RG_U2_BC11_SW_EN BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
+#define PA6_RG_U2_SQTH GENMASK(3, 0)
+#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020)
#define P2C_RG_USB20_GPIO_CTL BIT(9)
@@ -165,9 +167,10 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
writel(tmp, port_base + U3P_U2PHYDTM0);
}
- /* DP/DM BC1.1 path Disable */
tmp = readl(port_base + U3P_USBPHYACR6);
- tmp &= ~PA6_RG_U2_BC11_SW_EN;
+ tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
+ tmp &= ~PA6_RG_U2_SQTH;
+ tmp |= PA6_RG_U2_SQTH_VAL(2);
writel(tmp, port_base + U3P_USBPHYACR6);
tmp = readl(port_base + U3P_U3PHYA_DA_REG0);