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| author | M Chetan Kumar <m.chetan.kumar@linux.intel.com> | 2022-02-10 18:34:45 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-02-13 14:55:28 +0300 |
| commit | 1f52d7b622854b8bd7a1be3de095ca2e1f77098e (patch) | |
| tree | ac8432ad3174813c258564f15b7a47f9134de6bc /drivers/net/wwan/iosm/iosm_ipc_mmio.c | |
| parent | f126ec9d6e57729b3f7fad5d0e38bacfb81c8254 (diff) | |
| download | linux-1f52d7b622854b8bd7a1be3de095ca2e1f77098e.tar.xz | |
net: wwan: iosm: Enable M.2 7360 WWAN card support
This patch enables Intel M.2 7360 WWAN card support on
IOSM Driver.
Control path implementation is a reuse whereas data path
implementation it uses a different protocol called as MUX
Aggregation. The major portion of this patch covers the MUX
Aggregation protocol implementation used for IP traffic
communication.
For M.2 7360 WWAN card, driver exposes 2 wwan AT ports for
control communication. The user space application or the
modem manager to use wwan AT port for data path establishment.
During probe, driver reads the mux protocol device capability
register to know the mux protocol version supported by device.
Base on which the right mux protocol is initialized for data
path communication.
An overview of an Aggregation Protocol
1> An IP packet is encapsulated with 16 octet padding header
to form a Datagram & the start offset of the Datagram is
indexed into Datagram Header (DH).
2> Multiple such Datagrams are composed & the start offset of
each DH is indexed into Datagram Table Header (DTH).
3> The Datagram Table (DT) is IP session specific & table_length
item in DTH holds the number of composed datagram pertaining
to that particular IP session.
4> And finally the offset of first DTH is indexed into DBH (Datagram
Block Header).
So in TX/RX flow Datagram Block (Datagram Block Header + Payload)is
exchanged between driver & device.
Signed-off-by: M Chetan Kumar <m.chetan.kumar@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/wwan/iosm/iosm_ipc_mmio.c')
| -rw-r--r-- | drivers/net/wwan/iosm/iosm_ipc_mmio.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/net/wwan/iosm/iosm_ipc_mmio.c b/drivers/net/wwan/iosm/iosm_ipc_mmio.c index f09e5e77a2a5..63eb08c43c05 100644 --- a/drivers/net/wwan/iosm/iosm_ipc_mmio.c +++ b/drivers/net/wwan/iosm/iosm_ipc_mmio.c @@ -10,6 +10,7 @@ #include <linux/slab.h> #include "iosm_ipc_mmio.h" +#include "iosm_ipc_mux.h" /* Definition of MMIO offsets * note that MMIO_CI offsets are relative to end of chip info structure @@ -71,8 +72,9 @@ void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio) ver = ipc_mmio_get_cp_version(ipc_mmio); cp_cap = ioread32(ipc_mmio->base + ipc_mmio->offset.cp_capability); - ipc_mmio->has_mux_lite = (ver >= IOSM_CP_VERSION) && - !(cp_cap & DL_AGGR) && !(cp_cap & UL_AGGR); + ipc_mmio->mux_protocol = ((ver >= IOSM_CP_VERSION) && (cp_cap & + (UL_AGGR | DL_AGGR))) ? MUX_AGGREGATION + : MUX_LITE; ipc_mmio->has_ul_flow_credit = (ver >= IOSM_CP_VERSION) && (cp_cap & UL_FLOW_CREDIT); |