diff options
| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2020-03-24 17:13:58 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-03-25 02:36:37 +0300 |
| commit | 2283a02b67d41251a80857121e36845161fc57b5 (patch) | |
| tree | e185ee31e81736c7570bbcc17ac1b7e6be968b05 /drivers/net/phy/mscc/mscc.h | |
| parent | 148aa2a86c7a7db88b911f4efd63547bcec94710 (diff) | |
| download | linux-2283a02b67d41251a80857121e36845161fc57b5.tar.xz | |
net: phy: mscc: consolidate a common RGMII delay implementation
It looks like the VSC8584 PHY driver is rolling its own RGMII delay
configuration code, despite the fact that the logic is mostly the same.
In fact only the register layout and position for the RGMII controls has
changed. So we need to adapt and parameterize the PHY-dependent bit
fields when calling the new generic function.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/mscc/mscc.h')
| -rw-r--r-- | drivers/net/phy/mscc/mscc.h | 28 |
1 files changed, 9 insertions, 19 deletions
diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index d983d3af66d6..030bf8b600df 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -161,25 +161,15 @@ enum rgmii_clock_delay { /* Extended Page 2 Registers */ #define MSCC_PHY_CU_PMD_TX_CNTL 16 -#define MSCC_PHY_RGMII_SETTINGS 18 -#define RGMII_SKEW_RX_POS 1 -#define RGMII_SKEW_TX_POS 4 - -/* RGMII skew values, in ns */ -#define VSC8584_RGMII_SKEW_0_2 0 -#define VSC8584_RGMII_SKEW_0_8 1 -#define VSC8584_RGMII_SKEW_1_1 2 -#define VSC8584_RGMII_SKEW_1_7 3 -#define VSC8584_RGMII_SKEW_2_0 4 -#define VSC8584_RGMII_SKEW_2_3 5 -#define VSC8584_RGMII_SKEW_2_6 6 -#define VSC8584_RGMII_SKEW_3_4 7 - -#define MSCC_PHY_RGMII_CNTL 20 -#define RGMII_RX_CLK_DELAY_MASK 0x0070 -#define RGMII_RX_CLK_DELAY_POS 4 -#define RGMII_TX_CLK_DELAY_MASK 0x0007 -#define RGMII_TX_CLK_DELAY_POS 0 +/* RGMII setting controls at address 18E2, for VSC8572 and similar */ +#define VSC8572_RGMII_CNTL 18 +#define VSC8572_RGMII_RX_DELAY_MASK 0x000E +#define VSC8572_RGMII_TX_DELAY_MASK 0x0070 + +/* RGMII controls at address 20E2, for VSC8502 and similar */ +#define VSC8502_RGMII_CNTL 20 +#define VSC8502_RGMII_RX_DELAY_MASK 0x0070 +#define VSC8502_RGMII_TX_DELAY_MASK 0x0007 #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21 #define MSCC_PHY_WOL_MID_MAC_ADDR 22 |