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authorBjorn Andersson <bjorn.andersson@linaro.org>2022-03-23 06:32:55 +0300
committerJakub Kicinski <kuba@kernel.org>2022-03-25 03:48:02 +0300
commitffba2123e1714a27e9362fda57c42155dda37efc (patch)
tree3fa7e395a1edf08a05623956770a444c5a2351b7 /drivers/net/ethernet/stmicro/stmmac
parent169e77764adc041b1dacba84ea90516a895d43b2 (diff)
downloadlinux-ffba2123e1714a27e9362fda57c42155dda37efc.tar.xz
net: stmmac: dwmac-qcom-ethqos: Enable RGMII functional clock on resume
When the Qualcomm ethqos driver is properly described in its associated GDSC power-domain, the hardware will be powered down and loose its state between qcom_ethqos_probe() and stmmac_init_dma_engine(). The result of this is that the functional clock from the RGMII IO macro is no longer provides and the DMA software reset in dwmac4_dma_reset() will time out, due to lacking clock signal. Re-enable the functional clock, as part of the Qualcomm specific clock enablement sequence to avoid this problem. The final clock configuration will be adjusted by ethqos_fix_mac_speed() once the link is being brought up. Fixes: a7c30e62d4b8 ("net: stmmac: Add driver for Qualcomm ethqos") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-and-reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20220323033255.2282930-1-bjorn.andersson@linaro.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 0cc28c79cc61..835caa15d55f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -487,6 +487,13 @@ static int ethqos_clks_config(void *priv, bool enabled)
dev_err(&ethqos->pdev->dev, "rgmii_clk enable failed\n");
return ret;
}
+
+ /* Enable functional clock to prevent DMA reset to timeout due
+ * to lacking PHY clock after the hardware block has been power
+ * cycled. The actual configuration will be adjusted once
+ * ethqos_fix_mac_speed() is invoked.
+ */
+ ethqos_set_func_clk_en(ethqos);
} else {
clk_disable_unprepare(ethqos->rgmii_clk);
}