diff options
| author | Voon Weifeng <weifeng.voon@intel.com> | 2021-04-06 04:32:50 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-04-08 00:24:23 +0300 |
| commit | 017d6250ad719d3ddab9070446db1e9fd4ba4a65 (patch) | |
| tree | feb970022b5575dd53ff849ed06d2c154bfab4b5 /drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | |
| parent | 56f15e2cb1f77fbcf9df38de7e5dcb4b37070196 (diff) | |
| download | linux-017d6250ad719d3ddab9070446db1e9fd4ba4a65.tar.xz | |
stmmac: intel: Enable SERDES PHY rx clk for PSE
EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
sequence and vice versa.
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h index e723096c0b15..542acb8ce467 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h @@ -14,6 +14,7 @@ /* SERDES defines */ #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */ +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */ #define SERDES_RST BIT(2) /* Serdes Reset */ #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/ #define SERDES_PWR_ST_SHIFT 4 |