diff options
| author | Antoine Ténart <antoine.tenart@free-electrons.com> | 2017-08-25 16:24:46 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-08-26 06:10:42 +0300 |
| commit | ec15ecdee5eb9e33a565e1e8eaef39fd4de565cb (patch) | |
| tree | f5552d2fd3726c42f78b892ad84fd6c41180ade3 /drivers/net/ethernet/marvell | |
| parent | 49107fcbf436bb37861a924b7ec190a92fb95e36 (diff) | |
| download | linux-ec15ecdee5eb9e33a565e1e8eaef39fd4de565cb.tar.xz | |
net: mvpp2: fix the packet size configuration for 10G
The MVPP22_XLG_CTRL1_FRAMESIZELIMIT define is used as an offset, but is
defined as BIT(0). Updated its name to contains "OFFS" as in offset and
fix its value using the offset value, 0.
Reported-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Fixes: 76eb1b1de5b6 ("net: mvpp2: set maximum packet size for 10G ports")
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell')
| -rw-r--r-- | drivers/net/ethernet/marvell/mvpp2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 7fa251bf91ae..fea9ae5b70ba 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -367,7 +367,7 @@ #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) #define MVPP22_XLG_CTRL1_REG 0x104 -#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT BIT(0) +#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff #define MVPP22_XLG_CTRL3_REG 0x11c #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) @@ -4669,7 +4669,7 @@ static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) val = readl(port->base + MVPP22_XLG_CTRL1_REG); val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << - MVPP22_XLG_CTRL1_FRAMESIZELIMIT; + MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; writel(val, port->base + MVPP22_XLG_CTRL1_REG); } |