Merge tag 'mtd/for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD updates from Miquel Raynal:
 "MTD changes:

   - parsers: ofpart: add workaround for #size-cells 0

   - dt-bindings: partitions: Fix partition node name pattern

   - dataflash: remove duplicate SPI ID table

  Raw NAND core changes:

   - Check the data only read pattern only once

   - Prepare the late addition of supported operation checks

   - Support for sequential cache reads

   - Fix nand_chip kdoc

  Raw NAND driver changes:

   - Fsl_elbc: Propagate HW ECC settings to HW

   - Marvell: Add missing layouts

   - Pasemi: Don't use static data to track per-device state

   - Sunxi:
      - Fix the size of the last OOB region
      - Remove an unnecessary check
      - Remove an unnecessary check
      - Clean up chips after failed init
      - Precompute the ECC_CTL register value
      - Embed sunxi_nand_hw_ecc by value
      - Update OOB layout to match hardware

   - tmio_nand: Remove driver

   - vf610_nfc: Use regular comments for functions

  SPI-NAND driver changes:

   - Add support for AllianceMemory AS5F34G04SND

   - Macronix: use scratch buffer for DMA operation

  NAND ECC changes:

   - Mediatek:
      - Add ECC support fot MT7986 IC
      - Add compatible for MT7986
      - dt-bindings: Split ECC engine with rawnand controller

  SPI NOR changes:

   - Misc core fixes

  SPI NOR driver changes:

   - Spansion: Minor fixes"

* tag 'mtd/for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (33 commits)
  mtd: parsers: ofpart: add workaround for #size-cells 0
  mtd: rawnand: sunxi: Precompute the ECC_CTL register value
  mtd: rawnand: sunxi: Embed sunxi_nand_hw_ecc by value
  mtd: rawnand: sunxi: Update OOB layout to match hardware
  mtd: spi-nor: Sort headers alphabetically
  mtd: spi-nor: Fix shift-out-of-bounds in spi_nor_set_erase_type
  mtd: nand: ecc-mtk: Add ECC support fot MT7986 IC
  dt-bindings: mtd: mediatek,nand-ecc-engine: Add compatible for MT7986
  dt-bindings: mtd: Split ECC engine with rawnand controller
  mtd: rawnand: fsl_elbc: Propagate HW ECC settings to HW
  mtd: spinand: Add support for AllianceMemory AS5F34G04SND
  dt-bindings: mtd: partitions: Fix partition node name pattern
  mtd: spi-nor: Create macros to define chip IDs and geometries
  mtd: spi-nor: spansion: Make CFRx reg fields generic
  mtd: spi-nor: spansion: Consider reserved bits in CFR5 register
  mtd: spi-nor: core: fix implicit declaration warning
  mtd: spinand: macronix: use scratch buffer for DMA operation
  mtd: rawnand: Fix nand_chip kdoc
  mtd: rawnand: vf610_nfc: use regular comments for functions
  mtd: rawnand: Support for sequential cache reads
  ...

1 files changed, 25 insertions, 3 deletions

diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-mtk.c
index 9f9b201fe706..c75bb8b80cc1 100644
--- a/drivers/mtd/nand/ecc-mtk.c
+++ b/drivers/mtd/nand/ecc-mtk.c
@@ -40,6 +40,10 @@
 #define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
 #define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
 
+#define ECC_ERRMASK_MT7622	GENMASK(4, 0)
+#define ECC_ERRMASK_MT2701	GENMASK(5, 0)
+#define ECC_ERRMASK_MT2712	GENMASK(6, 0)
+
 struct mtk_ecc_caps {
 	u32 err_mask;
 	u32 err_shift;
@@ -79,6 +83,10 @@ static const u8 ecc_strength_mt7622[] = {
 	4, 6, 8, 10, 12
 };
 
+static const u8 ecc_strength_mt7986[] = {
+	4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
+};
+
 enum mtk_ecc_regs {
 	ECC_ENCPAR00,
 	ECC_ENCIRQ_EN,
@@ -451,7 +459,7 @@ unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
 EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
 
 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
-	.err_mask = 0x3f,
+	.err_mask = ECC_ERRMASK_MT2701,
 	.err_shift = 8,
 	.ecc_strength = ecc_strength_mt2701,
 	.ecc_regs = mt2701_ecc_regs,
@@ -462,7 +470,7 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
 };
 
 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
-	.err_mask = 0x7f,
+	.err_mask = ECC_ERRMASK_MT2712,
 	.err_shift = 8,
 	.ecc_strength = ecc_strength_mt2712,
 	.ecc_regs = mt2712_ecc_regs,
@@ -473,7 +481,7 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
 };
 
 static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
-	.err_mask = 0x1f,
+	.err_mask = ECC_ERRMASK_MT7622,
 	.err_shift = 5,
 	.ecc_strength = ecc_strength_mt7622,
 	.ecc_regs = mt7622_ecc_regs,
@@ -483,6 +491,17 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
 	.pg_irq_sel = 0,
 };
 
+static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 = {
+	.err_mask = ECC_ERRMASK_MT7622,
+	.err_shift = 8,
+	.ecc_strength = ecc_strength_mt7986,
+	.ecc_regs = mt2712_ecc_regs,
+	.num_ecc_strength = 11,
+	.ecc_mode_shift = 5,
+	.parity_bits = 14,
+	.pg_irq_sel = 1,
+};
+
 static const struct of_device_id mtk_ecc_dt_match[] = {
 	{
 		.compatible = "mediatek,mt2701-ecc",
@@ -493,6 +512,9 @@ static const struct of_device_id mtk_ecc_dt_match[] = {
 	}, {
 		.compatible = "mediatek,mt7622-ecc",
 		.data = &mtk_ecc_caps_mt7622,
+	}, {
+		.compatible = "mediatek,mt7986-ecc",
+		.data = &mtk_ecc_caps_mt7986,
 	},
 	{},
 };