diff options
| author | Hans Verkuil <hverkuil@xs4all.nl> | 2015-06-10 08:45:45 +0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2015-06-10 16:01:16 +0300 |
| commit | 95a86e43183eeeef72105372074f4ef127b27807 (patch) | |
| tree | 21b0b47d8e8243a7816dc114ffef21edcea0e7a4 /drivers/media/pci/cobalt | |
| parent | 64657066f51355461b634a0aa6a1171d50c355c9 (diff) | |
| download | linux-95a86e43183eeeef72105372074f4ef127b27807.tar.xz | |
[media] cobalt: fix 64-bit division
There are still some 64-bit division problems in the cobalt code.
Replace it by div_u64.
[mchehab@osg.samsung.com: folded with an additional diff sent by
Hans via a priv e-mail]
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Reported-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat (limited to 'drivers/media/pci/cobalt')
| -rw-r--r-- | drivers/media/pci/cobalt/cobalt-cpld.c | 14 | ||||
| -rw-r--r-- | drivers/media/pci/cobalt/cobalt-v4l2.c | 2 |
2 files changed, 8 insertions, 8 deletions
diff --git a/drivers/media/pci/cobalt/cobalt-cpld.c b/drivers/media/pci/cobalt/cobalt-cpld.c index 5a28d9b28dc9..e83f5c9f7e7d 100644 --- a/drivers/media/pci/cobalt/cobalt-cpld.c +++ b/drivers/media/pci/cobalt/cobalt-cpld.c @@ -240,8 +240,8 @@ static const struct multiplier multipliers[] = { bool cobalt_cpld_set_freq(struct cobalt *cobalt, unsigned f_out) { const unsigned f_xtal = 39170000; /* xtal for si598 */ - unsigned long long dco; - unsigned long long rfreq; + u64 dco; + u64 rfreq; unsigned delta = 0xffffffff; unsigned i_best = 0; unsigned i; @@ -253,12 +253,12 @@ bool cobalt_cpld_set_freq(struct cobalt *cobalt, unsigned f_out) for (i = 0; i < ARRAY_SIZE(multipliers); i++) { unsigned mult = multipliers[i].mult; - unsigned d; + u32 d; - dco = (unsigned long long)f_out * mult; + dco = (u64)f_out * mult; if (dco < DCO_MIN || dco > DCO_MAX) continue; - d = ((dco << 28) + f_xtal / 2) % f_xtal; + div_u64_rem((dco << 28) + f_xtal / 2, f_xtal, &d); if (d < delta) { found = 1; i_best = i; @@ -267,10 +267,10 @@ bool cobalt_cpld_set_freq(struct cobalt *cobalt, unsigned f_out) } if (!found) return false; - dco = (unsigned long long)f_out * multipliers[i_best].mult; + dco = (u64)f_out * multipliers[i_best].mult; n1 = multipliers[i_best].n1 - 1; hsdiv = multipliers[i_best].hsdiv - 4; - rfreq = (dco << 28) / f_xtal; + rfreq = div_u64(dco << 28, f_xtal); clock_ctrl = cpld_read(cobalt, SI570_CLOCK_CTRL); clock_ctrl |= S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_FPGA_CTRL; diff --git a/drivers/media/pci/cobalt/cobalt-v4l2.c b/drivers/media/pci/cobalt/cobalt-v4l2.c index 6fb8812990f4..b40c2d141b58 100644 --- a/drivers/media/pci/cobalt/cobalt-v4l2.c +++ b/drivers/media/pci/cobalt/cobalt-v4l2.c @@ -327,7 +327,7 @@ static int cobalt_start_streaming(struct vb2_queue *q, unsigned int count) iowrite32(clk_freq / 1000000, &clkloss->ref_clk_cnt_val); /* The lower bound for the clock frequency is 0.5% lower as is * allowed by the spec */ - iowrite32((((u64)bt->pixelclock * 995) / 1000) / 1000000, + iowrite32(div_u64(bt->pixelclock * 995, 1000000000), &clkloss->test_clk_cnt_val); /* will be enabled after the first frame has been received */ iowrite32(bt->width * bt->height, &fw->active_length); |