diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-05-31 22:18:39 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-06-01 16:45:18 +0300 |
| commit | fba99b1ab7bde41c1eb00431df37b9237be3681e (patch) | |
| tree | e376a61afc3a86f83195c8dfb49248c9e2f97aca /drivers/gpu | |
| parent | 04514c14678e760e17e3cd44c553ade1bf3bef06 (diff) | |
| download | linux-fba99b1ab7bde41c1eb00431df37b9237be3681e.tar.xz | |
drm/i915: Parse VRR capability from VBT
VBT seems to have an extra flag for VRR vs. not. Let's consult
that for eDP panels.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-2-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_bios.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_types.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_vrr.c | 22 |
3 files changed, 23 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index d80d147154b4..31520d08e33e 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1292,6 +1292,8 @@ parse_power_conservation_features(struct drm_i915_private *i915, const struct bdb_lfp_power *power; u8 panel_type = panel->vbt.panel_type; + panel->vbt.vrr = true; /* matches Windows behaviour */ + if (i915->vbt.version < 228) return; @@ -1312,6 +1314,9 @@ parse_power_conservation_features(struct drm_i915_private *i915, if (i915->vbt.version >= 232) panel->vbt.edp.hobl = power->hobl & BIT(panel_type); + + if (i915->vbt.version >= 233) + panel->vbt.vrr = power->vrr_feature_enabled & BIT(panel_type); } static void diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9723ae448c0b..09a664c51a4a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -294,6 +294,8 @@ struct intel_vbt_panel_data { unsigned int lvds_dither:1; unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ + bool vrr; + u8 seamless_drrs_min_refresh_rate; enum drrs_type drrs_type; diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 081e52dd6c4e..04250a0fec3c 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -15,19 +15,29 @@ bool intel_vrr_is_capable(struct intel_connector *connector) struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_dp *intel_dp; - if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && - connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) - return false; - - intel_dp = intel_attached_dp(connector); /* * DP Sink is capable of VRR video timings if * Ignore MSA bit is set in DPCD. * EDID monitor range also should be atleast 10 for reasonable * Adaptive Sync or Variable Refresh Rate end user experience. */ + switch (connector->base.connector_type) { + case DRM_MODE_CONNECTOR_eDP: + if (!connector->panel.vbt.vrr) + return false; + fallthrough; + case DRM_MODE_CONNECTOR_DisplayPort: + intel_dp = intel_attached_dp(connector); + + if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd)) + return false; + + break; + default: + return false; + } + return HAS_VRR(i915) && - drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; } |